The Ethernet SerDes IP solutions address the performance, power, and area requirements of today’s mobile, consumer, and enterprise (infrastructure) markets with extensive standard support for the latest PCI Express® (PCIe®), Ethernet and USB specifications. Available for both low-power mobile applications and high-performance computing applications, the Ethernet SerDes PHY IP is pre-integrated with Cadence controllers and equipped with extensive test features for superior interoperability and the lowest risk path to SoC success.
Ethernet SerDes - 16Gbps and 10Gbps multi-protocol SerDes PHY
Overview
Key Features
- Wide range of protocols that support networking, HPC, and applications
- Low-latency, long-reach, and low-power modes
- Multi-Link PHY—mix protocols within the same macro
- EyeSurf —non-destructive on-chip oscilloscope
- Extensive set of isolation, test modes, and loop-backs including APB and JTAG
- Supports 16-bit, 20-bit, and 32-bit PIPE and non-PIPE interfaces
- Selectable serial pin polarity reversal for both transmit and receive paths
Block Diagram
Deliverables
- PMA Hard Macro
- PCS-BIST Soft Macro
- Datasheet
- SoC integration guide
- Optional design integration and bring-up support services
Technical Specifications
Maturity
In Production
GLOBALFOUNDRIES
In Production:
12nm
Related IPs
- Ethernet PCS IP - Integrates MAC IP to a broad range of PHY and SerDes IP
- 10Gbps Multi-Link and Multi-Protocol PCIe 3.1 PHY IP for TSMC
- 16Gbps multi-protocol programmable SerDes PHY in UMC 28HPC+
- 10Gbps Multi-Link and Multi-Protocol PCIe 4.0 PHY IP for SMIC
- Multiprotocol SerDes PMA
- 8G Multiprotocol Serdes IP, Silicon Proven in SMIC 14SF+