16G Multiprotocol SerDes PHY IP
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4
IP
from 3 vendors
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4)
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16G Multi-Protocol SerDes (MPS) PHY - Samsung 14nm
- Duplex lane configurations of x2, x4, and x38
- Transmit swing of at least 800mV differential peak-to-peak for MR & LR, 360mv for SR
- Support for AC-coupled interfaces
- Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
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16G Multi-Protocol SerDes (MPS) PHY - GLOBALFOUNDRIES 12nm
- Duplex lane configurations of x2, x4, and x38
- Transmit swing of at least 800mV differential peak-to-peak for MR & LR, 360mv for SR
- Support for AC-coupled interfaces
- Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
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16G SerDes in 28nm
- ? Configurable data rate up to 16Gbps
- ? Multiple 8 lanes transceiver
- ? Internal high performance Frac-N PLL, support SSC
- ? 32bit parallel data bus
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16G Multiproocol Serdes IP, Silicon Proven in TSMC 28HPC+
- Multiple lanes transceiver with data rate from 1Gbps to 16Gbps
- Transceiver version including both receiver and transmitter
- Transmitter only version
- 40bit/32bit/20bit/16bit selectable parallel data bus