IP Catalog > 112G Long Reach SerDes PHY 7nm

112G Long Reach SerDes PHY 7nm IP

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Compare 9 IP from 1 vendors (1 - 9)
  • 112G PHY, TSMC N7 x4, North/South (vertical) poly orientation
    • Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
    • Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
    • Supports IEEE 802.3ck and OIF standards electrical specifications
    • Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
    Block Diagram -- 112G PHY, TSMC N7 x4, North/South (vertical) poly orientation
  • 112G Ethernet PHY, TSMC N7 x4, North/South (vertical) poly orientation
    • Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
    • Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
    • Supports IEEE 802.3ck and OIF standards electrical specifications
    • Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
    Block Diagram -- 112G Ethernet PHY, TSMC N7 x4, North/South (vertical) poly orientation
  • 112G Ethernet PHY, TSMC N7 x2, North/South (vertical) poly orientation
    • Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
    • Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
    • Supports IEEE 802.3ck and OIF standards electrical specifications
    • Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
    Block Diagram -- 112G Ethernet PHY, TSMC N7 x2, North/South (vertical) poly orientation
  • 112G Ethernet PHY, TSMC N7 x1, North/South (vertical) poly orientation
    • Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
    • Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
    • Supports IEEE 802.3ck and OIF standards electrical specifications
    • Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
    Block Diagram -- 112G Ethernet PHY, TSMC N7 x1, North/South (vertical) poly orientation
  • 112G Ethernet PHY, TSMC N6 x2, North/South (vertical) poly orientation
    • Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
    • Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
    • Supports IEEE 802.3ck and OIF standards electrical specifications
    • Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
    Block Diagram -- 112G Ethernet PHY, TSMC N6 x2, North/South (vertical) poly orientation
  • 112G Ethernet PHY, TSMC N6 x1, North/South (vertical) poly orientation
    • Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
    • Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
    • Supports IEEE 802.3ck and OIF standards electrical specifications
    • Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
    Block Diagram -- 112G Ethernet PHY, TSMC N6 x1, North/South (vertical) poly orientation
  • 112G Ethernet PHY, TSMC N5 x4, North/South (vertical) poly orientation
    • Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
    • Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
    • Supports IEEE 802.3ck and OIF standards electrical specifications
    • Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
    Block Diagram -- 112G Ethernet PHY, TSMC N5 x4, North/South (vertical) poly orientation
  • 112G Ethernet PHY, TSMC N3P x4 1.2V, North/South (vertical) poly orientation
    • Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
    • Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
    • Supports IEEE 802.3ck and OIF standards electrical specifications
    • Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
    Block Diagram -- 112G Ethernet PHY, TSMC N3P x4 1.2V, North/South (vertical) poly orientation
  • 112G Ethernet LRM PHY, TSMC N3P x4, North/South (vertical) poly orientation
    • Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
    • Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
    • Supports IEEE 802.3ck and OIF standards electrical specifications
    • Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
    Block Diagram -- 112G Ethernet LRM PHY, TSMC N3P x4, North/South (vertical) poly orientation
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