LPDDR6 Controller IP
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LPDDR6 Controller IP
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Simulation VIP for LPDDR6
- This Verification IP (VIP) is intended for modeling the upcoming JEDEC Low-Power Memory Device, LPDDR6 design specification.
- It provides a mature, highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification.
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LPDDR6/5X/5 Controller IP
- Supports JEDEC standard LPDDR6, LPDDR5X and LPDDR5 SDRAMs
- Support for data rates up to 14.4 Gbps for LPDDR6, 10.67 Gbps for LPDDR5X, and 6.4 Gbps for LPDDR5
- Multiport Arm® AMBA® interface AXI™4 with managed QoS or single-port host interface to the DDR controller
- DFI 5.2 compliant interface to Synopsys LPDDR6/5X/5 PHY
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LPDDR6 Verification IP
- The LPDDR6 Verification IP provides an effective & efficient way to verify the LPDDR6 components of an IP or SoC.
- The VIP is lightweight, featuring easy-to-use plug-and-play components, so there is no impact on the design cycle time.
