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MIPI C-PHY IP

As part of the MIPI (Mobile Industry Processor Interface) standard, MIPI C-PHY IP provides optimized signal integrity and low power consumption, making it ideal for high-speed applications such as imaging, video, and sensor communication. With its unique encoding scheme, MIPI C-PHY IP can support multiple data lanes, ensuring faster and more efficient data transfer while minimizing power usage.

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Compare 68 MIPI C-PHY IP from 9 vendors (1 - 10)
  • MIPI C-PHY - 28nm, 14nm, 8nm, 5nm, 4nm
    • The MIPI C-PHY IP is a hard-macro PHY for CSI RX. IO pads and ESD structures are included.
    • In addition, extensive built-in self-test features, such as loopback and scan, are supported.
    • It offers a cost-effective and low power solution.
    Block Diagram -- MIPI C-PHY - 28nm, 14nm, 8nm, 5nm, 4nm
  • MIPI CPHY v1.1 Analog Interface
    • The MIPI CPHY V1.1 improves throughput over a bandwidth-limited channel, allowing more data without an increased signaling clock.
    • It is intended to be used for camera interface (CSI-2 v1.3) and display interface (DSI-2 v1.0).
    • The signaling interface uses a 3-phase transceiver that encodes 3-bit symbols over 3 wires. This is different from the two-wire differential “lane” used in D-PHY.
    Block Diagram -- MIPI CPHY v1.1 Analog Interface
  • MIPI C-PHY
    • The C-PHY configuration consists of up to three lane modules and is based on 3-Phase symbol encoding technology, delivering 2.28 bits per symbol over three-wire trios and targeting a maximum rate of 2.5 Gsps, 5.7Gbps.
    • The C-PHY is partitioned into a digital module – CIL (Control and Interface Logic) and a mixed-signal module. The PHY IP is provided as a combination of soft IP views (RTL, and STA Constraints) for the digital module, and hard IP views (GDSII/CDL/LEF/LIB) for the mixed-signal module.
    Block Diagram -- MIPI C-PHY
  • MIPI CPHY Verification IP
    • Full MIPI CPHY Transmitter and Receiver functionality.
    • Supports 2.0 MIPI CPHY Specifications.
    • Supports up to 32 trio lanes.
    • Supports both serial and PPI functionality testing.
    Block Diagram -- MIPI CPHY Verification IP
  • C-PHY Verification IP
    • Compliant to MIPI C-PHY Specification version 2.1 with PPI interface.
    • Supports all configuration of a data lane module as specified in Figure 6 of C-PHY specification version 2.1 for Data Lane Module (MFAA & SFAA, MFAE & SFAE, MFEA & SFEA, MFAN & SFAN, MFEE & SFEE, MFEN & SFEN).
    • Supports ULPS, Triggers and LPDT in low power escape mode.
    • Bi-directional Data lane turnaround is supported for escape mode
    Block Diagram -- C-PHY Verification IP
  • MIPI C-PHY v1.2 D-PHY v2.1 RX 3 trios/4 Lanes - TSMC7FF 1.8V, North/South Poly Orientation
    • Compliant with the MIPI D-PHY specification, v2.1
    • 4 Lanes in D-PHY mode up to 6.5Gb/s per lane
    • Compliant with the MIPI C-PHY specification, v2.0
    • 3 trios in C-PHY mode up to 6.5Gs/s per trio
    Block Diagram -- MIPI C-PHY v1.2 D-PHY v2.1 RX 3 trios/4 Lanes - TSMC7FF 1.8V, North/South Poly Orientation
  • MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes - TSMC7FF 1.8V, N/S, for Automotive, ASIL B Random, AEC-Q100 Grade 2
    • Compliant with the MIPI D-PHY specification, v2.1
    • 4 Lanes in D-PHY mode up to 6.5Gb/s per lane
    • Compliant with the MIPI C-PHY specification, v2.0
    • 3 trios in C-PHY mode up to 6.5Gs/s per trio
    Block Diagram -- MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes - TSMC7FF 1.8V, N/S, for Automotive, ASIL B Random, AEC-Q100 Grade 2
  • MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes - TSMC6FFC 1.8V, North/South Poly Orientation
    • Compliant with the MIPI D-PHY specification, v2.1
    • 4 Lanes in D-PHY mode up to 6.5Gb/s per lane
    • Compliant with the MIPI C-PHY specification, v2.0
    • 3 trios in C-PHY mode up to 6.5Gs/s per trio
    Block Diagram -- MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes - TSMC6FFC 1.8V, North/South Poly Orientation
  • MIPI C-PHY v1.2 D-PHY v2.1 RX 3 trios/4 Lanes - TSMC6FF 1.8V, North/South Poly Orientation
    • Compliant with the MIPI D-PHY specification, v2.1
    • 4 Lanes in D-PHY mode up to 6.5Gb/s per lane
    • Compliant with the MIPI C-PHY specification, v2.0
    • 3 trios in C-PHY mode up to 6.5Gs/s per trio
    Block Diagram -- MIPI C-PHY v1.2 D-PHY v2.1 RX 3 trios/4 Lanes - TSMC6FF 1.8V, North/South Poly Orientation
  • MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes - TSMC16FFC 1.8V, North/South Poly Orientation
    • Compliant with the MIPI D-PHY specification, v2.1
    • 4 Lanes in D-PHY mode up to 6.5Gb/s per lane
    • Compliant with the MIPI C-PHY specification, v2.0
    • 3 trios in C-PHY mode up to 6.5Gs/s per trio
    Block Diagram -- MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes - TSMC16FFC 1.8V, North/South Poly Orientation
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