MIPI PHY IP
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MIPI PHY IP
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MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
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MIPI C-PHY/D-PHY Combo RX+ IP 4.5Gsps/4.5Gbps in TSMC N5
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
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MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- Compliant to MIPI Alliance Standard for C-PHY specification Version 1.2
- Compliant to MIPI Alliance Standard for D-PHY specification Version 1.2
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MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- Compliant to MIPI for C-PHY specification Version 1.2
- Compliant to MIPI for D-PHY specification Version 1.2
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MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- Compliant to MIPI Alliance Standard for D-PHY specification Version 2.1, 1.2, 1.1
- Supports standard PHY transceiver compliant to MIPI Specification
- Supports standard PPI interface compliant to MIPI Specification
- Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
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MIPI D-PHY Tx IP, Silicon Proven in TSMC 22ULP
- DSI PCS :
- The Register Bank is accessible through a standard AMBA-APB slave interface, providing access to the DSI PHY registers for configuration and control.
- Host_adapter: remapping PPI Signal with lane control and phy_adapter block;
- Lane_ctrl block (clklane_ctrl/datalane0_ctrl/datalane1_ctrl/datalane2_ctrl/datalane3_ctrl)
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MIPI C-PHY/D-PHY Combo TX+ IP 4.5Gsps/4.5Gbps in TSMC N5
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
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MIPI C-PHY/D-PHY Combo RX IP 4.5Gsps/4.5Gbps in TSMC N7
- Dual mode PHY Supports MIPI Alliance Specification D-PHYv2.5 & C-PHYv2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHYmode
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MIPI C-PHY/D-PHY Combo Universal IP, 4.5Gsps/4.5Gbps in TSMC 22ULP
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v1.2
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
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MIPI D-PHY Universal IP in UMC 28HPC+
- Supports MIPI Alliance Specification for D-PHY Version 2.5
- Consists of 1 Clock lane and 4 Data lanes
- Embedded, high performance, and highly programmable PLL
- Supports both low-power mode and high speed mode with integrated SERDES
