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Clocking IP for UMC

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Compare 734 Clocking IP for UMC from 14 vendors (1 - 10)
  • Crystal Oscillators
    • The crystal oscillator macros are available in a wide range of industry-standard quartz crystals and MEMS resonators operating in the fundamental mode in the 32 kHz to 80 MHz range.
    • These oscillators, which are both power and area efficient, have a programmable transconductance to allow users to find the optimal balance between jitter and power consumption.
    Block Diagram -- Crystal Oscillators
  • 5MHz-35MHz Low Power Crystal Oscillator - TSMC 0.18µ
    • 4MHz-35MHz Frequency range.
    • No external bias or limit resistors required.
    • Current optimization for best power at frequency.
    • Amplitude control loop.
    • The OSCI pad input can be used as a CMOS input for test.
    • Uses single 1.8V supply.
    • Enable/power down provision.
    Block Diagram -- 5MHz-35MHz Low Power Crystal Oscillator - TSMC 0.18µ
  • Phase-locked loop frequency synthesizer
    • CMOS UMC 65 nm
    • Integer-N frequency synthesizer with good phase noise performance
    • Guaranteed frequency range 550…750 MHz
    • Wide continuous loop frequency divider ratio range (16..2047 with step 1) allow to cover frequency range using different reference frequency
    Block Diagram -- Phase-locked loop frequency synthesizer
  • Free running oscillators
    • Compact and low power
    • No external components
    • Baseline CMOS logic process masks only
    • Excellent frequency precision over PVT after trimming
    Block Diagram -- Free running oscillators
  • 10MHz to 50MHz fractional-N PLL synthesizer
    • UMC 22nm ULP technology
    • 1.8V IO power supply
    • Double 0.8/1.0V Core power supply
    • Embedded low noise bias
    Block Diagram -- 10MHz to 50MHz fractional-N PLL synthesizer
  • Ultra low power 32.768 kHz crystal oscillator
    • UMC 55nm eFlash CMOS technology
    • Input Voltage 1.2V
    • Fixed 32.768kHz output frequency
    Block Diagram -- Ultra low power 32.768 kHz crystal oscillator
  • Low Voltage, Low Power Fractional-N PLLs
    • Low power, suitable for IoT applications
    • Good jitter, suitable for clocking digital logic.
    • Extremely small die area (< 0.005 sq mm), using a ring oscillator
    • Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
    Block Diagram -- Low Voltage, Low Power Fractional-N PLLs
  • Fractional-N PLLs for Performance Computing
    • Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
    • Extremely small die area (< 0.005 sq mm), using a ring oscillator
    • Output frequency can be from 1 to 400 times the input reference, up to 4GHz
    • Reference clock from 10MHz to 500MHz
    Block Diagram -- Fractional-N PLLs for Performance Computing
  • Fractional-N PLL for Performance Computing in UMC40LP
    • Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
    • Extremely small die area (< 0.02 sq mm), using a ring oscillator
    • Output frequency can be from 1 to 400 times the input reference, up to 4GHz
    • Reference clock from 10MHz to 500MHz
    Block Diagram -- Fractional-N PLL for Performance Computing in UMC40LP
  • General Purpose Fractional-N PLLs
    • Low power, suitable for logic clocking applications
    • Extremely small die area, using a ring oscillator
    • Twelve bits fractional resolution
    Block Diagram -- General Purpose Fractional-N PLLs
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