Phase-locked loop frequency synthesizer

Overview

PLL is an automatic control system adjusting controlled oscillator frequency to be equal to reference oscillator frequency multiplied by a given integer ratio. Frequency adjustment is carried out by using negative feedback. A phase detector compares a controlled oscillator output with a reference signal. The result is a charge pump current output that supplies feedback low-pass filter and converted to a voltage for controlled oscillator adjustment.
Clock divider is used to generate signals with specified frequency.
This block designed for CMOS UMC 65 nm technology.

Key Features

CMOS UMC 65 nm
Integer-N frequency synthesizer with good phase noise performance
Guaranteed frequency range 550…750 MHz
Wide continuous loop frequency divider ratio range (16..2047 with step 1) allow to cover frequency range using different reference frequency
Wide continuous reference frequency divider ratio range (1..31 with step 1) allow to use high reference frequency or reach high frequency resolution
Integrated lock detector circuit with high accuracy
Integrated loop filter with adjustment ability
No external components required
Low power consumption
Portable to other technologies (upon request)

Applications

Portable transmitters and transceivers

Deliverables

Schematic or NetList
Abstract model (.lef and .lib files)
Layout view (optional)
Behavioral model (Verilog)
Extracted view (optional)
GDSII
DRC, LVS, antenna report
Test bench with saved configurations (optional)
Documentation

Technical Specifications

Foundry, Node

UMC CMOS 65 nm

Maturity

silicon proven

Availability

Now

UMC

Silicon Proven: 65nm LL

Request Info