Standard cell IP for TSMC
Welcome to the ultimate
Standard cell IP
for
TSMC
hub! Explore our vast directory of
Standard cell IP
for
TSMC
All offers in
Standard cell IP
for
TSMC
Filter
Compare
6
Standard cell IP
for
TSMC
from
3
vendors
(1
-
6)
Filter:
- 28nm
-
Standard Cell
- Dolphin offers an extensive array of Standard Cell libraries that have been methodically tested and verified in silicon for each process technology supported.
- More than 3500 fully customizable cells are available, and each has been optimized for speed, routability, power and density, in order to maximize performance and wafer yield while lowering overall SoC cost.
-
PMK Library IPs at TSMC 28HPC+ Process
- Power-gating cells for domain shutdown
- Isolation cells to prevent unknown states that come from unpowered domains
- Data retention flip-flops
- Always-on cells powered by retention supply rail
- Level shifter cells for multiple voltage domain
-
LPKT Library IPs at TSMC 28HPC+ Process
- Multi-bit flip-flops to save power and area
- Fine grain cells provide a variety of drive strengths to improve design PPA (Power, Performance, Area)
-
ECO Library IPs at TSMC 28HPC+ Process
- Ease-of-use, compatible to industrial EDA flow
- Combinational cells (Inverter, Buffer, NAND, NOR, AOI/OAI, XOR/XNR)
- Sequential cells (Scan Flip-flop, and Latch)
-
Standard Cell Library in TSMC (12nm~180nm)
- -Ultra-High-Density Standard Cell Library (HDSC) for highest density, lowest cost and lowest power
- -General Purpose Standard Cell Library (GPSC) for general purpose logic with balanced PPA
- -Ultra-High Speed Standard Cell Library (HSSC) for the optimized performance in the critical path
- -Low Leakage Standard Cell library (LLSC) for ultra-low-leakage