Memory Interfaces IP for TSMC
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- 16nm
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Memory Compiler in TSMC (16nm,22nm,28nm,40nm,55nm,90BCD+,110nm,152nm,180BCD)
- Synchronous read/write operation
- Low leakage current and lower operation power consumption
- Minimum metal layer requirement: 4/3 metal layers
- High density layout structure and small area design
-
7 way DDR combo
- Full DDR4 capability
- Full DDR3 / DDR3L / DDR3U capability
- Full LPDDR4 capability
- Full LPDDR3 capability