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Memory Controller/PHY IP for TSMC

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Compare 497 Memory Controller/PHY IP for TSMC from 16 vendors (1 - 10)
  • ONFi PHY 4.0 (FPHY+MDLL+SDLL Regulator) (Silicon Proven in TSMC 28HPC+)
    • Support ONFi 4.0 IO Electrical Specification
    • Support Legacy up to 50MHz
    • Support NV-DDR2 with operating frequency up to 533Mbps
    • Support NV-DDR3 with operating frequency up to 800Mbps
    Block Diagram -- ONFi PHY 4.0 (FPHY+MDLL+SDLL Regulator) (Silicon Proven in TSMC 28HPC+)
  • TSMC CLN3FFP HBM4 PHY
    • IGAHBMZ03A is a High Bandwidth Memory 4 Physical  Layer (HBM4 PHY) that is compliant with JEDEC HBM4 DRAM Specification JESD270-4.
    • Fabricated in the TSMC 3 nm Advanced process node (N3P), it supports the data rate up to 12 Gbps per data pin in the DDR PHY Interface (DFI)-like 1:4 clock frequency ratio (HBM4 controller clock: WDQS = 1:4).
    Block Diagram -- TSMC CLN3FFP HBM4 PHY
  • Serial ATA (SATA) PHY Transceiver IP
    • SMS6000 is a fully integrated CMOS transceiver that handles the low level Serial ATA protocol and signaling.
    • It contains all necessary Clock synthesis, Clock Recovery, Serializer, Deserializer, Comma detect for 8B/10B encoded data and Frame alignment functionalities.
    Block Diagram -- Serial ATA (SATA) PHY Transceiver IP
  • GDDR6 PHY IP for 12nm
    • JEDEC JESD250 compliant GDDR6 support
    • X16 mode, X8 mode, and pseudo-channel mode
    • Low frequency RDQS mode support
    Block Diagram -- GDDR6 PHY IP for 12nm
  • TSMC CLN7FF HBM3 PHY
    • IGAHBMX03A is a HBM3 (High Bandwidth Memory) PHY IP compliant to the JEDEC HBM3 DRAM Specification Rev 0.95.
    • Built on TSMC 7nm process node, it supports data rate up to 7200 Mbps per data pin with DFI 1:4 clock frequency ratio (controller clock : WCK = 1:4).
    Block Diagram -- TSMC CLN7FF HBM3 PHY
  • TSMC N3P 1.8V IO Platform supporting cells
    • Compliant with eMMC 5.1 HS400, SD 6.0 SDR104, DDR50, JESD8-7a (1.2V/1.8V) and JESD8c.01 (3.3V)
    • Fully integrated hard macro with high speed IOs and DLL/delay lines
    • Fine resolution DLL/delay lines for HS400 strobe and HS200/SDR104 auto-tuning
    • Easy to integrate with the highly optimized Synopsys SD/eMMC Host Controller IP, providing a complete low risk solution
    Block Diagram -- TSMC N3P 1.8V IO Platform supporting cells
  • M31 eMMC/SDIO at TSMC 28HPC+ Process
    • Supports HS400 (400Mbps), HS200 (200Mbps), High-speed DDR (52Mbps) and etc.
    • Consisting of driver, receiver & pull-up/down resistors
    • Power-sequence free
    • Provides multi-driving-strength selection
    Block Diagram -- M31 eMMC/SDIO at TSMC 28HPC+ Process
  • ONFI 4.1 PHY IP (Silicon Proven in TSMC 12FFC)
    • Support ONFi 4.1 IO Electrical Specification
    • Support Legacy up to 50MHz
    • Support NV-DDR2 up to 533Mbps
    • Support NV-DDR3 up to 1200Mbps
    Block Diagram -- ONFI 4.1 PHY IP (Silicon Proven in TSMC 12FFC)
  • GDDR6 PHY
    • Single configuration supports one GDDR6 device per channel (coplanar) or two GDDR6 devices per channel (clamshell)
    •  DFI PHY Independent Mode for initialization and training
    • Adaptive and continuous timing recovery
    •  Internal and external datapath loop-back modes
    •  Transmit crosstalk cancelation of immediate neighbors
    •  Per-bit DFE, CTLE, and FFE equalization
    Block Diagram -- GDDR6 PHY
  • DDR5/4 PHY for TSMC 7nm
    • Application optimized configurations for fast time to delivery and lower risk
    • Memory controller interface complies with DFI standards up to 5.0
    • Internal and external datapath loop-back modes
    • Per-bit deskew on read and write datapath
    Block Diagram -- DDR5/4 PHY for TSMC 7nm
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