IP stack IP for TSMC
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Ultra Low Latency 10G TCP Endpoint
- The TCP Endpoint implements a full, reliable streaming network stack in FPGA logic.
- It allows applications in logic to be directly connected to Internet Protocol (IP) interfaces by opening, maintaining, and closing TCP Connections via Ethernet to other hardware or software endpoints.
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1G TCP Offload Engine TOE Very Low Latency (TOE)
- Ideal for high performance and mid performance specialized, differentiable ASICs or FPGAs for Network security or Network infrastructure applications
- Less than 4000 Xilinx slices, Altera ALMs or 150,000 ASIC gates + on-chip memory
- Fully integrated 100 M bit/1-G bit high performance EMAC.
- Scalable MAC Rx FIFOs and Tx FIFOs make it ideal for optimizing system performance.
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10 Gb/s full HW stack UDP/IP Transmitter/Receiver
- Transmits UDP with IP packets up to 10Gb/s, with 10G Ethernet protocol to host
- Receives UDP with IP packets up to 1Gb/s with 10G Ethernet protocol from host
