Clocking IP for TSMC

Compare 7 Clocking IP for TSMC from 1 vendors (1 - 7)

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Core Powered Wide Range Programmable Integer PLL on TSMC CLN2P
- Electrically Programmable PLL with Fractional-N divide and Spread Spectrum Clock Generation
- Entirely core voltage powered, needs no analog supply voltage
- Wide Ranges of Input and Output Frequency for diverse clocking needs
- Very fine precision: near 1 part per billion resolution
18-40MHz Crystal Oscillator on TSMC CLN2P
- Crystal Oscillator pad macro that supports industry standard crystals
- Uses standard CMOS transistors
- Crystal Oscillation Mode: Fundamental
- Power down option for IDDQ testing
PCIe Gen4/5/6 Class Low Jitter LC PLL on TSMC CLN2P
- High performance design emphasis for meeting low jitter requirements in PCIe Gen4 & Gen5 applications
- Implemented with Analog Bits’ proprietary LC architecture
- Low power consumption
- Spread Spectrum Clock Generation (SSCG) and tracking capability
High Performance 20GHz C2C PLL on TSMC CLN2P
- Electrically Programmable PLL for multiple applications
- Wide Ranges of Output Frequency for diverse clocking needs
- Implemented with Analog Bits’ proprietary architecture
- Low power consumption
Differential Clock Receiver to CMOS on TSMC CLN2P
Differential Clock Receiver to CML on TSMC CLN2P
- Differential clock receiver
- CML differential output to chip core
- Wide Ranges of input frequencies for diverse clocking needs
- Implemented with Analog Bits’ proprietary architecture
Wide Range Programmable Integer PLL on TSMC CLN2P
- Electrically Programmable PLL for multiple applications
- Wide Ranges of Input and Output Frequency for diverse clocking needs
- Implemented with Analog Bits’ proprietary architecture
- Small area footprint