Interface IP
Welcome to the ultimate Interface Protocol IP hub! Explore our vast directory of Interface Protocol IP such as Ethernet, USB, PCIe, DDR, HBM, CXL, HDMI, MIPI, Die-to-Die UCIe, and much more
Interface protocols enable chip-to-chip, board-to-board, or box-to-box connectivity in system designs.
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Interface IP
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3,159
Interface IP
from 190 vendors
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HBM4 Memory Controller
- Supports HBM4 memory devices
- Supports all standard HBM4 channel densities (up to 32 Gb)
- Supports up to 10 Gbps/pin
- Refresh Management (RFM) support
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PCIe 7.0 Controller with AXI
- Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
- Scalable data path
- Advanced PIPE modes and port bifurcation
- Supports multiple virtual channels (VCs) in FLIT and non-FLIT modes
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Ethernet Enterprise Switch/Router IP Core - Efficient and Massively Customizable
- Full wire-speed on all ports and all Ethernet frame sizes.
- Store and forward shared memory architecture.
- Support for jumbo packets up to 32739 bytes.
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UCIe PHY & D2D Adapter
- 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
- UCIe v1.1 specification
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USB 2.0 PHY GlobalFoundaries 12nm, 22nm, 28nm, 40nm
- Complies with USB specifications Rev. 2.0 and 1.1
- Complies with UTMI+ specification Level 3, Rev. 1.0
- Supports 480Mb/s (HS), 12Mb/s (FS) and 1.5MB/s (LS) serial data transmission rates
- Supports 8-bit unidirectional Parallel Interface Engine (PIE) bus for HS, FS and LS modes, and Serial Interface Engine (SIE) for FS and LS modes
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USB 2.0 PHY TSMC 5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm, 65nm, 130nm, 180nm
- Complies with USB specifications Rev. 2.0 and 1.1
- Complies with UTMI+ specification Level 3, Rev. 1.0
- Supports 480Mb/s (HS), 12Mb/s (FS) and 1.5MB/s (LS) serial data transmission rates
- Supports 8-bit unidirectional Parallel Interface Engine (PIE) bus for HS, FS and LS modes, and Serial Interface Engine (SIE) for FS and LS modes
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MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
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TSMC CLN4P 4nm DDR5 PHY - 6400Mbps
- Supports DDR5
- DFI 5.1 compliant
- Supports x4, x8 and x16 DRAMs
- Up to 72 bits wide and up to 4 ranks
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ReRAM NVM in 130nm CMOS, S130
- Technology: 130nm, SkyWater S130
- Mask Adder: 2
- Supply Voltage: 1.8V Read, 1.8V+3.3/3.6V Program
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LPDDR5X DDR Memory Controller
- JEDEC LPDDR5X/LPDDR5 devices compatible
- Data rates up to 8533Mbps
- Multiple ARM AMBA AXI4/AHB/APB & Custom interfaces
