Receiver/Transmitter IP for GLOBALFOUNDRIES

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Compare 3 Receiver/Transmitter IP for GLOBALFOUNDRIES from 2 vendors (1 - 3)
  • LVDS Deserializer IP
    • The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology.
    • Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The De-serializer is highly integrated and requires no external components.
    Block Diagram -- LVDS Deserializer IP
  • Dual RSDS Transmitter, 24/18-bit color, 40-300Mb/s (SVGA/UXGA/full HDTV) LCD & Plasma display
    • • 20 to 150Mhz Pixel rate ( 40 to 300 Mb/s SDR input, 40 to 300 Mb/s DDR output)
    • • Complies with RSDS “Intra-Panel” Interface Specification rev1.0, May 2003.
    • • 1P6M layout structure based on 0.18um 1P6M generic logic process.
    • • 3.3V/1.8V 10% supply voltage, -40/+125C
  • LVDS Transmitter 1250Mb/s, 800Mhz clock with RSDS support
    • • 1P6M layout structure based on 0.18um 1P6M 1.8V
    • generic logic process.
    • • 3.3V/1.8V ±10% supply voltage, -40/+125°C temperature.
    • • IEEE Standard 1596.3-1996 and ANSI/TIA/EIA- 644-A Specifications.
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