The Tessent Embedded Analytics solution can be used to produce health and operational metrics throughout the lifecycle of an SoC. Embedded software based on the Tessent Embedded SDK can drive the Tessent Embedded Analytics smart monitors to create a self-contained on-chip monitoring system.
Leveraging embedded non-intrusive instrumentation such as bus monitors, NoC monitors, and CPU debug modules, data can be continuously collected and analyzed on chip, before results and key data points are exported and analyzed centrally. The Tessent Embedded Analytics instruments enable full transaction-level visibility of traffic on buses with a wide range of measurements, analytics and statistics gathering. All of these are highly configurable and include “logic analyzer” style controls and dependencies, local buffering and cross-triggering.
All Tessent Embedded Analytics monitors (IPs), can be accessed via a dedicated, secure communication infrastructure. Embedded software can drive the system via an AXI interface to create a self-contained on-chip monitoring system. Non-intrusive debug and monitoring using an off-chip host or debugger is facilitated through USB 2, USB 3, JTAG, or Aurora interfaces.
Tessent in-life monitoring
Overview
Key Features
- Bus Monitor enables complete, transaction-level visibility of SoC bus activity across all major standards (AXI, ACE, OCP)
- Network-on-Chip (NOC) Monitor provides transaction-level visibility for devices using the Arm AMBA 5 Coherent Bus Interface (CHI)
- Status Monitors provides embedded logic analyzer capability
- Processor Analytics provides run-control, performance monitoring, cross triggering, and event driven control of embedded processors.
- Static instrumentation provides a nonintrusive mechanism for conde instrumentation.
- Direct Memory Access (DMA) analytic module provide direct memory access to system memory from debug host.
Benefits
- Observe if your SoC behaves as it was meant to
- Enable continuous monitoring and fleet analytics
- Root-cause performance degradations and memory corruption
Deliverables
- Parameterized soft core (Verilog RTL)
- Available UVM verification IP
- Tessent Embedded SDK software development kit
Technical Specifications
Maturity
In silicon
Availability
Now
Related IPs
- Voltage Detect Vdet=2.5V Vhys=0.1V, generate a high/low level logic for a precise power supply monitoring system; UMC 90nm SP/RVT LowK Logic Process
- Voltage Detect Vdet1=2.8V,Vhys1=0.1V, Vdet2=2.6V, Vhys2=0.1V.Vdet2 rsie delay>10ms, fall delay<1ms. Generate high/low level logic for a precise power supply monitoring system; UMC 55nm eFlash Process
- Tessent RISC-V trace and debug
- Process Detector (For DVFS and monitoring process variation), TSMC N5
- Voltage Monitor with Digital Output (Multi-domain supply monitoring), TSMC N5
- PVT Controller (Series 5) (Sub-system for complete PVT monitoring), TSMC N5