PCIe Gen5/4 Retimer
Overview
Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retimer. An important capability of a Physical Layer protocol aware Retimer is to execute the Phase 2/3 of the equalization procedure in each direction. A maximum of two Retimers are permitted between an Upstream and a Downstream Port.
Key Features
- Compliant with PCIE Gen5/4 Specs.
- Forward mode supported.
- Execution mode for Equalization, Loopback and Compliance are supported.
- X1, X2, X4, X8, X16 lanes supported.
- Lane bifurcation supported.
- Lane polarity thru register control.
- PIPE 40bit Serdes interfaces.
- APB interface for register configurations.
- Lane deskew supported.
- Support for L1 states.
- SKP OS add/removal.
- SRIS mode supported.
- No equalization support thru configuration.
- De-emphasis negotiation support at 5GT/s.
- EI inferences in all modes.
- Automatic adjustment of data rates in conjunction with upstream and downstream devices.
- Automatic adjustment of link width in conjunction with upstream and downstream devices.
Block Diagram
Deliverables
- Verilog soft IP
- Sample testbench
Technical Specifications
Availability
Immediate