The MXL-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PHY v1.1.
The IP can be configured as a MIPI Master or MIPI Slave optimized for CSI-2 (Camera Serial Interface), and DSI(Display Serial Interface) applications.
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.
MIPI D-PHY Universal IP in TSMC 40ULP
Overview
Key Features
- Consists of 1 Clock lane and up to 2 Data lanes.
- Supports MIPI® Alliance Specification for D-PHYSM Version 1.1.
- Supports both high speed and low-power modes.
- 80 Mbps to 1.5 Gbps data rate in high speed mode
- 10 Mbps data rate in low-power mode.
- High Speed Serializers and Deserializers included.
- Low power dissipation.
- Loopback testability support.
- Optional resistance termination calibrator.
Benefits
- Supports both MIPI CSI-2 and MIPI DSI, as a transmitter and receiver
Block Diagram
Applications
- Mobile
- Displays
- Cameras/Sensors
- IoT
- VR/AR/MR
- Consumer electronics
- Automotive
Deliverables
- Specifications
- GDSII
- LVS netlist
- LEF file
- IBIS Model
- Verilog Model
- Timing Model
- Integration Guidelines
- RTL
- Documentation
- One year support
Technical Specifications
Foundry, Node
TSMC, 40ULP
Maturity
Available Upon Request
Availability
Now
TSMC
Pre-Silicon:
40nm
LP
Related IPs
- MIPI D-PHY Universal IP in UMC 28HPC+
- MIPI D-PHY IP 4.5Gbps in TSMC N7
- I2C Controller IP – Slave, SCL Clock only, principally for configuring registers in mixed-signal ICs with low noise or low power requirements
- I2C Controller IP – Slave, SCL Clock, Parameterized FIFO, APB Bus. For low power requirements in I2C Slave Controller interface to CPU
- MIPI D-PHY
- MIPI D-PHY TX & RX + DSI & CSI Controllers