MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP 4.5Gsps/4.5Gbps

Overview

Key Features

• Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.1
• Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
• Consists of 3 Data lanes in C-PHY mode
• Embedded, high performance, and highly programmable PLL
• PLL supports SSC mode, Fractional mode, and Integer mode
• Supports both low-power mode and high speed mode with integrated SERDES
• 80 Mbps to 1.5 Gbps data rate per lane without skew calibration in D-PHY mode
• 4.5 Gbps data rate per lane with skew calibration in high speed D-PHY mode
• 80 Msps to 4.5 Gsps symbol rate per lane in high speed C-PHY mode
• Supports High Speed TX De-emphasis Equalization
• 10 Mbps data rate in low-power mode
• Low power dissipation
• Testability support including internal loopback
• Calibrator for resistance termination

Benefits

• The Mixel MIPI C/D-PHY IP not only shares the serial interface pins, but Mixel’s implementation also reuses all the MIPI D-PHY functional blocks for the MIPI C-PHY, minimizing area and leakage power.
• The CSI-2 TX+ is a Mixel proprietary configuration that is optimized to support full-speed production and in-system testing while minimizing area and leakage power.

Block Diagram

Applications

• Mobile
• Cameras/Sensors
• IoT
• VR/AR/MR
• Consumer electronics
• Automotive

Deliverables

• Specifications
• GDSII
• LVS netlist
• LEF file
• IBIS Model
• Verilog Model
• Timing Model
• Integration Guidelines
• RTL
• Documentation
• One year support

Technical Specifications