MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP in TSMC 40ULP

Overview

The MXL-CDPHY-CSI-2-TX+-40ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2.5 and C-PHY v2.0. The PHY can be configured as a MIPI Master supporting camera interface CSI-2. The PHY supports mobile, IoT, virtual reality, and automotive applications. The CSI-2 TX+ is a Mixel proprietary configuration that is optimized to support full-speed production and in-system testing while minimizing area and leakage power.

Key Features

Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
Consists of 1 Clock lane and 1 Data lanes in D-PHY mode
Consists of 1 Data Trio in C-PHY mode
Supports both low-power mode and high-speed mode with integrated SERDES
80 Mbps to 1.5 Gbps data rate per lane without skew calibration in D-PHY mode
2.5 Gbps data rate per lane with skew calibration in high-speed D-PHY mode
80 Msps to 2.5 Gsps symbol rate per lane in high-speed C-PHY mode
10 Mbps data rate in low-power mode
Low power dissipation
Testability support including internal loopback
Calibrator for resistance termination

Benefits

The Mixel MIPI C/D-PHY IP not only shares the serial interface pins, but Mixel’s implementation also reuses all the MIPI D-PHY functional blocks for the MIPI C-PHY, minimizing area and leakage power.
The CSI-2 TX+ is a Mixel proprietary configuration that is optimized to support full-speed production and in-system testing while minimizing area and leakage power.

Block Diagram

Applications

Mobile
Cameras/Sensors
IoT
VR/AR/MR
Consumer electronics
Automotive

Deliverables

Specifications
GDSII
LVS netlist
LEF file
IBIS Model
Verilog Model
Timing Model
Integration Guidelines
RTL
Documentation
One year support

Technical Specifications

Foundry, Node

TSMC, 40ULP

Maturity

Available Upon Request

Availability