LPDDR5 DFI Synthesizable Transactor

Overview

Key Features

• Compliant with DFI version 5.0 Specifications.
• Supports LPDDR5 devices compliant with JEDEC LPDDR5 SDRAM Standard JESD209-5.pdf, JESD209-5A and LPDDR5X (Draft).
• Supports for Read data bus inversion.
• Supports for Write data bus inversion.
• Supports for DFI disconnect during training.
• Supports for WCK Control interface.
• Supports write clock free running mode.
• Supports data copy low power function and write x operation.
• Supports for 2:1 and 4:1 CKR mode.
• Supports all data rates as per specification.
• Supports write data mask operation.
• Supports WCK2CK Sync operation.
• Supports deep sleep mode.
• Supports power down mode and self-refresh operation.
• Supports frequency set point operation.
• Supports programmable clock frequency of operation.
• Supports following training modes.
• Command bus training
• WCK2CK leveling
• WCK-DQ training
• Enhanced RDQS training mode
• Supports DRAM Clock disabling feature.
• Supports Error signaling
• Supports all types of timing and protocol violation detection
• Checks for following:
• Check-points include power on, initialization and power off rules
• State based rules, active command rules
• Read/Write command rules etc
• All timing violations

Benefits

• Compatible with testbench writing using SmartDV's VIP
• All UVM sequences/testcases written with VIP can be reused
• Runs in every major emulators environment
• Runs in custom FPGA platforms

Block Diagram



Deliverables

• Synthesizable transactors
• Complete regression suite containing all the LPDDR5 DFI testcases
• Examples showing how to connect various components, and usage of Synthesizable Transactor
• Detailed documentation of all DPI, class, task and function's used in verification env
• Documentation contains User's Guide and Release notes

Technical Specifications