This design is a ISDB-S3-LDPC-BCH Decoder IP, ready to license, verified and packaged, and supplied as a portable and synthesizable Verilog IP. The system was designed to be used in conjunction with a standard RF tuner.
The synchronization system is capable of all forms or synchronization, including frame, symbol, frequency synchronization, as well as clock recovery, from scattered pilots, and continual pilots.
Signal degradation due to fading channel in wireless systems is overcome using a combination of interleaving, BCH error correction, and Low Density Parity Check (LDPC).
The data bit chain demodulates the incoming data stream using either 2D log-likelihood ratio (LLR) demapping, or 1D LLR, depending on whether the constellation rotation is done in the
transmitter, or not. The LDPC block and the BCH decoder have short frame and normal frame types. The LDPC decoder uses the minimum-sum algorithm.
ISDB-S3-LDPC-BCH Decoder IP
Overview
Key Features
- Layered Decoding
- Minimum sum algorithm
- Soft decision decoding
- BCH decoder works on GF (2^16 ) and corrects up to t =12 errors
- ARIB STD-B44 2.0 standard compliant
- The code length Nldpc is 44880 bits for all the supported code rates
Benefits
- Low-power and low-complexity design
- LDPC decoder, Energy dispersal and BCH decoder
- Frame-to-frame on-the-fly configuration
- Configurable amount of LDPC decoding iterations for trading-off throughput and error correction performance
Deliverables
- Synthesizable Verilog
- System Model (Matlab) and documentation
- Verilog Test Benches
- Documentation
Technical Specifications
Maturity
In Production
Availability
Immediate