This high performance, fully programmable Reed Solomon Decoder IP Core is intended for use in a wide range of applications requiring forward error correction and can be targeted in any ASIC or FPGA technologies.
In channel coding redundancy is inserted in the transmitted information bit-stream. This redundant information is used in the decoder to eliminate the channel noise. The error correction capability of a FEC system is strongly depended on the amount of redundancy as well as on the coding algorithm itself. The Reed Solomon decoder receives an N symbol codeword consisting of a K symbol information block appended with 2T parity symbols, locates and corrects up to T possible symbol errors or up to 2T erasure errors anywhere in the codeword. If more than T symbol errors or 2T erasure errors are received then the decoder marks the codeword as uncorrectable.
ARCHITECTURE
The decoder is parameterized in terms of bits per symbol (2M), maximum codeword length (N) and maximum correction power (T). It also supports shortened codes by varying on the fly the NVAL and TVAL inputs. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for adaptive FEC applications. If NVAL=2M-1 then the code is non shortened. If NVAL is less than 2M-1 then the code is shortened. The effective code rate is NVAL / (NVAL-2TVAL). The implementation is very low latency, high speed with a simple interface for applications.
