The CMS0014 DVB-S2 (A)PSK Demodulator is a high-performance (A)PSK demodulator core intended for DVB-S2 and DVB-S2X forward link applications.
The demodulator is compatible with the ACM, VCM and CCM configurations of the DVB-S2 Standard including DVB-S2 extensions and is therefore suitable for the reception of DVB broadcast, DSNG, professional and broadband interactive services.
Operating symbol rate is programmed from a register and extends from approximately 40% of the master clock frequency down to an arbitrary low rate that is set through synthesis options. The range would normally be dictated by the application and, in particular, the phase noise characteristics of the radio system.
Carrier acquisition is performed in several stages starting with a coarse, stepped search. The search range and step size are programmed through registers and can be set to accommodate an arbitrary offset (within the sample rate bandwidth). Payload symbols are output as soft decisions after descrambling and the recovery of carrier phase, symbol timing and gain.
The CMS0014 is provided with a baseband I/Q radio interface compatible with zero-IF and near-zero-IF tuner modules. The interface performs automatic compensation of DC offsets and quadrature imbalances (phase and amplitude).
Tuner Rx gain control is provided through PDM output RxAGC. Further stages of gain control are implemented digitally within the demodulator.
The Decimation Filter stage suppresses wideband interference and restricts the sample rate bandwidth prior to matched (RRC) channel filtering and timing recovery. The combined response of the Decimation and Channel Filters allows the CMS0014 to tolerate up to +10dBc of adjacent channel interference at any supported symbol rate.
Three dedicated processors at the output of the Channel Filter handle the DVB-S2-specific demodulation functions:
Sync Processor. This is responsible for the recovery of initial Physical Layer (PL) frame synchronisation from the Start of Frame (SOF) sequence in each PL Header.
Header Processor. This is responsible for configuring the Payload Processor according to the received MODCOD/PLSCODE field. The arrival of a SOF sequence triggers the (BPSK) demodulation and decoding of the PL Header.
The MODCO/PLSCODE field defines the modulation format, FEC code rate and size of the frame payload.
Payload Processor. This delivers soft output symbols (unsliced constellation samples) to a separate LDPC Decoder after carrier phase correction, gain normalisation and PL descrambling.
Register Configuration
Static configuration and status monitoring is performed through a bank of registers. This would typically be driven from a processor interface connected to a CPU that is embedded on the same device or located off-chip.
Parameters accessible through this interface include:
- Nominal symbol and input carrier frequencies;
- Window and step sizes for the coarse carrier search;
- AGC and PLL configuration and status;
- Estimated signal-to-noise ratio (CNIR).
Important synchronisation events such as the acquisition of symbol timing lock or PL frame sync are signalled through the SyncEvents output. Some or all of these signals would typically be connected to the processor interface as sources of interrupt but might otherwise be polled as status indicators.
The Channel and Decimation Filters use hard-wired FIR filter coefficients that are generated during synthesis. FPGA platforms employing more than one Channel Filter configuration would normally store a different netlist for each filter used.
The option of programmable coefficients is available for ASIC and high-end FPGA platforms that have adequate (multiplier) resources.
Full details of the register interface are provided in the CMS0014 IP Guide document.
