Asynchronous FIFO alternate design
Overview
This version of an asynchronous FIFO eschews the traditional grey code counters for a more complete and secure transfer mechanism between clock domains
Key Features
- Configurable for width and depth
- Configurable for fallthrough
Deliverables
- verilog RTL and Testbench
Technical Specifications
Short description
Asynchronous FIFO alternate design
Vendor
Vendor Name
Maturity
Multiple Uses
Availability
Now
Related IPs
- Asynchronous FIFO with flags and depth counter
- I3C Controller IP – Master / Slave, Parameterized FIFO, APB Bus. I3C Basic Specification Design
- Slave I2C bus controller with FIFO
- Universal Asynchronous Receiver / Transmitter
- UART - Universal Asynchronous Receiver / Transmitter Core
- Universal Asynchronous Receiver/Transmitter Module