Slave I2C bus controller with FIFO

Overview

Key Features

• Conforms to v.3.0 of the I2C specification
• Slave operation
• Slave transmitter
• Slave receiver
• Supports 3 transmission speed modes
• Standard (up to 100 kb/s)
• Fast (up to 400 kb/s)
• Fast Plus (up to 1 Mb/s)
• High Speed (up to 3,4 Mb/s)
• Double buffering of RX/TX data
• Configurable RX and TX FIFOs up to 256 bytes each
• Configurable length of SCL, SDA lines glitch filtering
• Allows operation from a wide range of input clock frequencies
• Simple interface allows easy connection to microprocessor/microcontroller devices
• Interrupt generation
• User-defined data setup time
• Available system interface wrappers:
• AMBA - APB Bus
• Altera Avalon Bus
• Xilinx OPB Bus
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready

Benefits

• Getting a sillicon proven IP
• Rapid prototyping and time-to-market reduction
• Design risk elimination
• Development costs reduction
• Full customization
• Technological independence (VHDL and Verilog)
• Global sales network
• Professional service

Applications

• Embedded microprocessor boards
• Consumer and professional audio/video
• Home and automotive radio
• Low-power applications
• Communication systems
• Cost-effective reliable automotive systems

Deliverables

• HDL Source Code
• Testbench environment
• Automatic Simulation macros
• Tests with reference responses
• Synthesis scripts
• Technical documentation
• 12 months of technical support

Technical Specifications