Building Blocks IP

Compare 141 Building Blocks IP from 46 vendors (1 - 10)

IP cores for ultra-low power AI-enabled devices
- Ultra-fast Response Time
- Zero-latency Switching
- Low Power
Tessent RISC-V trace and debug
- Instruction trace
- Efficient packet format
- Fast profiling
- Multiple retirement
Multi Channel FIR Filter
- Multi Channel FIR filter
- Selectable data and coefficient widths
- Selectable number of data channels
- Selectable number of filter taps
Merge Sort Core
- Optimized design allows customers to target cost efficient FPGAs.
- Can be tailored to customer needs
- Fully synchronous design using only one clock
- Area/Power efficient architecture
Hardware NLM (Non-Local-Mean) Video Noise Reduction IP core
- parameterized search-window size
- parameterized number of bits per pixel
- efficient implementation
Power and Ground BondPads that include CC-100IP Digital and Switching Circuit Power Reduction Technology, Featuring 20% to 40% Total Dynamic Power Reduction
- 20% to 40% Digital and Dynamic Power Reduction
- Fits into any IC bondpad
CC-100IP-PI Power Integrity Enhancement IP
- Occupies the same on chip area as standard DCAPs with at least a 600X effective capacitance increase
- Up to a 36% Dynamic Power and RF Emissions Reduction
- On-Chip Cybersecurity Enhancement
- 25% Reduction in Capacitor ESL
ITU-T G729A Voice Codec Hardware Accelerator
- Voice codec capable of multi-channel 8kbps voice compression based on ITU-T G729A standard.
- Selective Channel initialization.
- AMBA bus support for easy SoC integration.
- Best performance/silicon area ratio available in the industry.
Fully Configurable Radix 2 FFT/IFFT Processor
- Radix-2 Fast Fourier Transform processor IP Core.
- Same IP core may be used to compute both FFT and IFFT transforms without any complexity overhead.
- Highly parameterizable/scalable design using generic I/O fixed point precision and generic internal calculations precision.
- Bit true Matlab script model is provided to aid core fixed point precision configuration for any target application.
High Throughput Additive White Gaussian Noise Generator
- High precision AWGN Channel emulator.
- Programmable Pseudo Random Generator(LFSR).
- Programmable number of output bits.
- Support of throughput rates up to 10 Gbps.