RGB to ITU-R 601/656 Encoder

Overview

The DB1892AXI RGB to CCIR 601 / CCIR 656 Encoder interfaces RGB data along with synchronization signals from a LCD Controller (or any LCD display timing & control unit) to a TFT LCD Panel by-way-of a CCIR 601 / CCIR 656 interface.

Figure 1 depicts the system view of the DB1892AXI RGB to CCIR 601 / CCIR 656 Encoder IP Core embedded within an integrated circuit device. The DB1892AXI RGB to CCIR 601 / CCIR 656 Encoder accepts 24-bit RGB data and VSYNC, HSYNC, and DE synchronization signals and converts the RGB & sync signals to the CCIR ITU-R BT.601 & BT.656 standards, for driving a CCIR 601 / CCIR 656 compliant LCD panel.

The DB1892AXI is a system-level IP Core which optional interfaces to the ARM AMBA AXI fabric for programming of internal parameters. The DB1892 is offered with AHB, OCP, PLB, and Avalon fabrics as options, as well as no fabric interface with hard-coding of the video transformation parameters.

The DB1892 interfaces to Digital Blocks’ DB9000 TFT LCD Controller, for a full system solution of transforming Frame Buffer RGB data to CCIR 601 / CCIR 656 standard video.

Key Features

  • The DB1892 performs the following video signal processing functions:
  • Color Space Converter - Inputs RGB 24-bit data and sync signals VSYNC, HSYNC, & Date Enable from a LCD Controller. The Color Space Converter converts the 4:4:4 sampled RGB pixels to component luma and chroma digital video 4:4:4 YCbCr.
  • Chroma Resampler - The Chroma Resampler down converts the 4:4:4 YCbCr to 4:2:2 YCbCr, in order to meet the ITU-R BT.601 requirements of the ITURBT. 656 Encoder.
  • BT.656 Encoder - Encodes the 4:2:2 YCbCr component digital video with synch signals to conform to the ITU-RBT.656 digital coding standard.

Benefits

  • The DB1892 RGB to CCIR 601 / 656 Encoder is a system-level IP integrating the Color Space Converter, Chroma Resampler, & BT.656 Encoder functions for full transformation from the RGB color space to the BT.656 4:2:2 Y’CbCr color space & BT.656 framing. The DB1892 supports the following bus interfaces for configuration:
  • AMBA 2.0 AHB Master, AHB Slave
  • AMBA 1.0 AXI , AXI4
  • CoreConnect PLB, OPB
  • Avalon, Qsys
  • OCP 2.2
  • PCI
  • Hard-coded parameters requiring no bus fabric interface

Block Diagram

RGB to ITU-R 601/656 Encoder Block Diagram

Deliverables

  • Verilog RTL Source or technology-specific netlist.
  • Comprehensive testbench suite with expected results.
  • Synthesis scripts.
  • Installation & Implementation Guide.
  • Technical Reference Manual.

Technical Specifications

Foundry, Node
IBM, LSI. TMSC, UMC, Tower, SMIC, STMicroelectronics, GlobalFoundries
Maturity
Successful in Company FPGA Kit Demo Reference Design, Customer Products
Availability
Immediately
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Semiconductor IP