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Compare 46 Other from 15 vendors (1 - 10)
  • MIMO Decoder
    • Includes QR Decomposition, Dynamic scale and  K-best Decoder
    • Fixed Depth K-Best Decoder (K=16)
    • Achieves close-to ML BER performance
    • Supports synchronized streams with different QAM (from BPSK to 64 QAM) dependent on MIMO mode
    • Supports square and non-square QAM
    Block Diagram -- MIMO Decoder
  • MIMO Sphere Decoder
    • Fixed Complexity Sphere Decoder providing fixed throughput
    • Achieves close-to ML BER performance
    • MATLAB and C model for – MIMO 2×2 and 4×4 – Can be modified to support other MIMO sizes – BPSK, 4-QAM, 16-QAM and 64-QAM
    • Efficient and optimized FPGA Architecture (4×4 MIMO, 16-QAM)
    Block Diagram -- MIMO Sphere Decoder
  • Decision tree inference core
    • So_ip_idt core can be used create a decision tree directly in hardware. It can create DTs with univarite, multivariate and non-linear tests.
    • Creating DTs directly in hardware results in the significant increase of DT inference speed, compared with the traditional software-based approach.
    Block Diagram -- Decision tree inference core
  • NCO Intel® FPGA IP Core
    • A numerically controlled oscillator (NCO) is a digital signal generator, which synthesizes a discrete-time, discrete-valued representation of a sinusoidal waveform
    • You can typically use NCOs in communication systems
    • In such systems, they are used as quadrature carrier generators in I-Q mixers, in which baseband data is modulated onto the orthogonal carriers in one of a variety of ways.
    Block Diagram -- NCO Intel® FPGA IP Core
  • Merge Sort Core
    • Optimized design allows customers to target cost efficient FPGAs.
    • Can be tailored to customer needs
    • Fully synchronous design using only one clock
    • Area/Power efficient architecture
    Block Diagram -- Merge Sort Core
  • High Throughput Additive White Gaussian Noise Generator
    • High precision AWGN Channel emulator.
    • Programmable Pseudo Random Generator(LFSR).
    • Programmable number of output bits.
    • Support of throughput rates up to 10 Gbps.
    Block Diagram -- High Throughput Additive White Gaussian Noise Generator
  • Cognitive Radio IP Core
    • Parameterisable Input bit width
    • Parameterisable FFT size
    • Parameterisable HMM window length
    Block Diagram -- Cognitive Radio IP Core
  • Tessent RISC-V trace and debug
    • Instruction trace
    • Efficient packet format
    • Fast profiling
    • Multiple retirement
    Block Diagram -- Tessent RISC-V trace and debug
  • Block Diagram -- Crest Factor reduction IP
  • Hardware NLM (Non-Local-Mean) Video Noise Reduction IP core
    • parameterized search-window size
    • parameterized number of bits per pixel
    • efficient implementation
    Block Diagram -- Hardware NLM (Non-Local-Mean) Video Noise Reduction IP core
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Semiconductor IP