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Decision tree inference core
- So_ip_idt core can be used create a decision tree directly in hardware. It can create DTs with univarite, multivariate and non-linear tests.
- Creating DTs directly in hardware results in the significant increase of DT inference speed, compared with the traditional software-based approach.
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NCO Intel® FPGA IP Core
- A numerically controlled oscillator (NCO) is a digital signal generator, which synthesizes a discrete-time, discrete-valued representation of a sinusoidal waveform
- You can typically use NCOs in communication systems
- In such systems, they are used as quadrature carrier generators in I-Q mixers, in which baseband data is modulated onto the orthogonal carriers in one of a variety of ways.
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Merge Sort Core
- Optimized design allows customers to target cost efficient FPGAs.
- Can be tailored to customer needs
- Fully synchronous design using only one clock
- Area/Power efficient architecture
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High Throughput Additive White Gaussian Noise Generator
- High precision AWGN Channel emulator.
- Programmable Pseudo Random Generator(LFSR).
- Programmable number of output bits.
- Support of throughput rates up to 10 Gbps.
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Cognitive Radio IP Core
- Parameterisable Input bit width
- Parameterisable FFT size
- Parameterisable HMM window length
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Tessent RISC-V trace and debug
- Instruction trace
- Efficient packet format
- Fast profiling
- Multiple retirement
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2D Edge Detector
- Single color plane input
- Configurable input data width
- Dynamically variable input frame size
- Dynamic active region selection
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Gamma Corrector
- Configurable number of color planes: 1 to 3
- Configurable number of bits per color plane: 4 to 12
- Option to specify gamma correction characteristics as an equation using a gamma value or by the actual mapping values of the look-up table
- Gamma correction look-up table can be run-time programmable
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Numerically Controlled Oscillator
- Supports single or multi channel operation up to 16 channels
- Run time variable phase increment input Δθ and phase offset input φ
- Up to 32-bit user-configurable phase resolution
- Up to 20-bit user-configurable quantizer resolution
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Correlator IP Core
- Supports 1 to 8 bit input data width
- Supports 1 to 256 channels
- Supports a correlation window from 8 to 2048 taps
- Supports oversampled input data from 2x to 8x
