Filter IP

RGB to ITU-R 601/656 Encoder

The DB1892AXI RGB to CCIR 601 / CCIR 656 Encoder interfaces RGB data along with synchronization signals from a LCD Controller (or any LCD display timing & control unit) to a TFT LCD Panel by-way-of a CCIR 601 / CCIR 656 interface.

2.56 MHz Digital filter

SGB25V technology
Build-in clock former
Test modes – digital data output
Operating with complex signal

LMS Adaptive Channel Equalizer

17-tap T-spaced complex-arithmetic LMS signed-error Channel Equalizer
Adaptation bandwidth control (mu, step size)

Serial FIR Filter

Serial Arithmetic for Reduced Resource Utilization
Variable Number of Taps up to 64
Data and Coefficients up to 32 Bits
Output Size Consistent with Data Size

Parallel FIR Filter

Variable number of taps up to 64
Data and coefficients up to 32 bits
Output size consistent with data size
Zero-latency operation

FIR Filter Generator

Direct Form 64-Tap FIR Filter: In the direct form FIR filter, the input samples are shifted into a shift register queue and each shift register is connected to a multiplier. The products from the multipliers are added together to get the FIR filter’s output sample. This example shows a 64-tap FIR filter using 16 sysDSP blocks and approximately 512 slices in the LatticeECP3 FPGA.
128-Tap Long Asymmetrical Filters Using Ladder Architecture: Using the ladder architecture, the FIR filter is split into sections each having the same coefficient set as if it was a single continuous filter chain. Instead of connecting the shifted data and the result outputs from the first section to the corresponding input of the next section, the ladder network connects a delayed version of the first stage input data to the second stage input data and sums a delayed version of the first stage sum output with the second stage sum output.
256-Tap Long Symmetrical Filters Using Ladder Architecture: The impulse response for most FIR filters is symmetric. This symmetry can generally be exploited to reduce the arithmetic requirements and produce area-efficient filter realizations. It is possible to use only half the multipliers for symmetric coefficients compared to that used for a similar filter with non-symmetric coefficients. An implementation for symmetric coefficients is shown in the figure below. The 256-tap long symmetrical filter example uses only 32 sysDSP slices, 2EBR and 3.5K slices.
Polyphase Interpolator FIR Filter Designs: The polyphase interpolation filter implements the computationally efficient 1-to-P interpolation filter where P is an integer greater than 1. The example below shows a design with an interpolation by 16 that uses 128 taps. This requires 8 polyphase filters (sub-filters) with 16 coefficients each.

2D FIR Filter

Single color plane
Single-rate, interpolating, and decimating filter configurations
Input frame size set at compile-time
Static or dynamic zoom and pan

Cascaded Integrator-Comb (CIC) Filter

1-32-bit Input Data Width
1-8 Cascaded Stages
1-4 Cycles Differential Delay, Run-time Programmable for Both Decimation and Interpolation
2-16,384 Decimation and Interpolation Sampling Rate Factor, Run-time Programmable Rates for Both Decimationand Interpolation

Distributed Arithmetic FIR (DA-FIR) Filter Generator

Variable number of taps up to 1024
Multi-channel support (up to 32 channels)
Polyphase interpolation/decimation filters
Halfband filters

FFT Compiler

Wide range of points sizes: 64, 128, 256, 512, 1024, 2048, 4096, 8192, and 16384
Choice of high-performance (streaming I/O) and low resource (burst I/O) versions
Run-time variable FFT point size
Forward, inverse or port-configurable forward/inverse transform modes