Filter IP
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32
Filter IP
from 18 vendors
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10)
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ASIP-1 FFT Engine
- Platform to design Application Specific Instruction Set Processors (ASIPs).
- Ideal for supporting multi-standard systems.
- Supports a wide range of complex DSP functions.
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ASIP-2 Programmable Filter Engine
- Platform to design Application Specific Instruction Set Processors (ASIPs).
- Ideal for supporting multi-standard systems.
- Supports a wide range of complex DSP functions
- The ASIP2 performs Fast Fourier Transform (FFT) to convert time domain signals to frequency domain signals for further processing. It supports FFT sizes from 4 to 8K.
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CIC Intel® FPGA IP Core
- The CIC Intel FPGA IP core implements a Cascaded integrator-comb (CIC) filter with data ports that are compatible with the Avalon® streaming (Avalon-ST) interface
- CIC filters (also known as Hogenauer filters) are computationally efficient for extracting baseband signals from narrow-band sources using decimation
- They also construct narrow-band signals from processed baseband signals using interpolation.
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RGB to ITU-R 601/656 Encoder
- The DB1892AXI RGB to CCIR 601 / CCIR 656 Encoder interfaces RGB data along with synchronization signals from a LCD Controller (or any LCD display timing & control unit) to a TFT LCD Panel by-way-of a CCIR 601 / CCIR 656 interface.
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2.56 MHz Digital filter
- SGB25V technology
- Build-in clock former
- Test modes – digital data output
- Operating with complex signal
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LMS Adaptive Channel Equalizer
- 17-tap T-spaced complex-arithmetic LMS signed-error Channel Equalizer
- Adaptation bandwidth control (mu, step size)
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Multi Channel FIR Filter
- Multi Channel FIR filter
- Selectable data and coefficient widths
- Selectable number of data channels
- Selectable number of filter taps
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TX & RX FIR Filter specifically to support DSP Application
- Synthesizable, technology-independent IP Core for FPGA/ASIC and SoC
- Coded with Verilog
- It support 2 type of filters, Equiripple and Root Rise Cosine (RRC)
- 16/12-bit Fixed-Point Representation/Operation (Imaginary and Real Number)
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Power and Ground BondPads that include CC-100IP Digital and Switching Circuit Power Reduction Technology, Featuring 20% to 40% Total Dynamic Power Reduction
- 20% to 40% Digital and Dynamic Power Reduction
- Fits into any IC bondpad
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CC-100IP-PI Power Integrity Enhancement IP
- Occupies the same on chip area as standard DCAPs with at least a 600X effective capacitance increase
- Up to a 36% Dynamic Power and RF Emissions Reduction
- On-Chip Cybersecurity Enhancement
- 25% Reduction in Capacitor ESL