UWB at IPSoC: a perfect reuse case study in-waiting
Developers of UWB products would benefit from strategically planning for IP Reuse
Reuse is often applied retrospectively and that can make it more complex, expensive, and time consuming than it otherwise needs to be. We help customers to benefit from reuse at any stage of product’s evolution and its migration to different technologies, nodes. But the fact is it is easier for you, the developer if it is part of a well-planned IP reuse design strategy and built into a long-term roadmap.
At the #IPSoC event last week, we saw the interest in Ultrawideband (UWB) – not a new technology – it’s been waiting in the wings for many years…but it is now starting to show its true potential. The U1 Apple chip released with some of its iPhones in 2019, includes UWB. And that’s always going to make the rest of the industry wonder if they should follow suit.
UWB is higher-frequency and broad spectrum radio technology. Its spatial awareness capabilities makes the radio ideal for applications in the Internet of Things, but now that the technology is suitable for portable, battery-powered devices, also high-speed large file transfer between devices. Automotive, industry 4.0, track and trace. There are plenty of market opportunities ripe for applying UWB.
To read the full article, click here
Related Semiconductor IP
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
- ASIL B Compliant MIPI CSI-2 CSE2 Security Module
- SHA-256 Secure Hash Algorithm IP Core
Related Blogs
- Case Study: Getting More Functionality from Existing Chips
- Case Study: Choosing the Right Benchmarks for the Job
- Case Study: Choosing the Right Benchmarks for the Job
- Case Study: Choose Your Desert Island Companion Wisely
Latest Blogs
- The Future of Storage: From eMMC to the Blazing Speeds of UFS 5.0
- Reimagining Chip Design - From Spec to Signoff with Cadence AI Super Agents
- The Architectural Evolution of 16GHz PLLs for Next-Gen AI and SerDes SoCs
- Considerations When Architecting Your Next SoC: NoCs with Arteris
- Implementing Dual-core Lockstep in the CHIPS Alliance VeeR EL2 RISC-V core for safety-critical applications