Using Synopsys Smart Monitors to Improve System Performance of Your Arm SoCs
In an SoC where AXI Bus is used to move a considerable amount of data, the performance of AXI Bus may become a bottleneck to your overall system performance. Increasing complexity and software content in SoCs is creating need to shift-left performance verification at pre-silicon using real life data payloads. Hardware-assisted verification platforms – Synopsys ZeBu® emulation system and Synopsys HAPS® FPGA prototyping system -are a necessity to run such large payloads.
How to Improve Throughput of AXI Bus
If a AXI Bus is being used for frequent bulk data transfer, achieving good throughput is very important. Throughput can be calculated by computing the sum of all data bytes (AxSIZE) in each beat (RVALID/BVALID) captured on the AXI interface during the observation window and dividing the sum by duration of observation window. A window showing low throughput generally doesn’t mean an issue, unless there was an expectation to move large amounts of data quickly.
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