Understanding Embedded USB2 (eUSB2) and its usage
December 21, 2023
The need for higher processing power and lower power consumption are driving processors and System on Chip (SoC) to more advanced lower process nodes. For SoCs operating at 1.2V supply that are suitable for mobile phones, tablets, and laptops, using USB2 interfaces is a challenge as it becomes difficult to support 3.3V IO cells. A low voltage USB2.0 solution is therefore required to address the gap.
The embedded USB2 (eUSB2) Physical Layer Supplement to the USB 2.0 Specification was created to address the need for a low voltage, power-efficient USB 2.0 PHY solution. It eliminates the need for 3.3V IO signaling in small process technologies.
Related Semiconductor IP
- eUSB2 v1.1 Dual-Role, repeater/native mode PHY, SamSung 28FDSOI, 1.8V, N/S orientation
- eUSB2 v1.1 Dual-Role, repeater/native mode PHY, SamSung 3LPE, 1.2V, N/S orientation
- eUSB2 v1.2 Dual-Role, repeater/native mode PHY, SamSung SF3P, 1.0V, N/S orientation
- eUSB2 v1.1 Dual-Role, repeater/native mode PHY, TSMC N7, 1.8V or 1.2V, N/S orientation
- eUSB2 v1.1 Dual-Role, repeater/native mode PHY, TSMC N5, 1.2V, N/S orientation
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- Understanding USB IP and Its Role in SOC Integration
- The Ubiquitous USB 2.0: Exploring Its Benefits and Widespread Adoption
- What Is the OSI Model, and How Can We Protect Its Critical Layers?
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