TSMC 40nm Yield Explained!
August 6, 2009
By far the most revealing session at the Design Automation Conference (DAC) last week was on Design for Manufacturing (DFM) entitled “DFM: Band-Aid or Competitive Weapon”. I first wrote about DFM in an EETimes article Taking the pain from design for manufacturability circa 2003, suggesting that companies who don’t design for manufacture will be Desperate For Money. John Cooley shortsightedly tagged DFM as Design For Marketing.
Related Semiconductor IP
- xSPI Multiple Bus Memory Controller
- MIPI CSI-2 IP
- PCIe Gen 7 Verification IP
- WIFI 2.4G/5G Low Power Wakeup Radio IP
- Radar IP
Related Blogs
- Blogging from Taiwan: TSMC and 40nm Yield
- Moore’s Law and 40nm Yield
- TSMC 28nm Yield Explained!
- The Truth of TSMC 28nm Yield!
Latest Blogs
- The Growing Importance of PVT Monitoring for Silicon Lifecycle Management
- Unlock early software development for custom RISC-V designs with faster simulation
- HBM4 Boosts Memory Performance for AI Training
- Using AI to Accelerate Chip Design: Dynamic, Adaptive Flows
- Locking When Emulating Xtensa LX Multi-Core on a Xilinx FPGA