TSMC 40nm Yield Explained!
August 6, 2009
By far the most revealing session at the Design Automation Conference (DAC) last week was on Design for Manufacturing (DFM) entitled “DFM: Band-Aid or Competitive Weapon”. I first wrote about DFM in an EETimes article Taking the pain from design for manufacturability circa 2003, suggesting that companies who don’t design for manufacture will be Desperate For Money. John Cooley shortsightedly tagged DFM as Design For Marketing.
Related Semiconductor IP
- SLVS Transceiver in TSMC 28nm
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Related Blogs
- Blogging from Taiwan: TSMC and 40nm Yield
- TSMC explains 40nm yield problems, metal-gate stacks and why 100 per cent utilisation is bad
- Moore’s Law and 40nm Yield
- TSMC on 40nm and 28nm yield issues
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