TSMC 40nm Yield Explained!
August 6, 2009
By far the most revealing session at the Design Automation Conference (DAC) last week was on Design for Manufacturing (DFM) entitled “DFM: Band-Aid or Competitive Weapon”. I first wrote about DFM in an EETimes article Taking the pain from design for manufacturability circa 2003, suggesting that companies who don’t design for manufacture will be Desperate For Money. John Cooley shortsightedly tagged DFM as Design For Marketing.
Related Semiconductor IP
- General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
- JPEG XL Encoder
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- ML-KEM Key Encapsulation & ML-DSA Digital Signature Engine
- MIPI SoundWire I3S Peripheral IP
Related Blogs
- Blogging from Taiwan: TSMC and 40nm Yield
- Moore’s Law and 40nm Yield
- The Truth of TSMC 28nm Yield!
- TSMC Gets 28nm Yield Up Over 80%