TSMC 40nm Yield Explained!
By far the most revealing session at the Design Automation Conference (DAC) last week was on Design for Manufacturing (DFM) entitled “DFM: Band-Aid or Competitive Weapon”. I first wrote about DFM in an EETimes article Taking the pain from design for manufacturability circa 2003, suggesting that companies who don’t design for manufacture will be Desperate For Money. John Cooley shortsightedly tagged DFM as Design For Marketing.
Related Semiconductor IP
- UFS 5.0 Host Controller IP
- PDM Receiver/PDM-to-PCM Converter
- Voltage and Temperature Sensor with integrated ADC - GlobalFoundries® 22FDX®
- 8MHz / 40MHz Pierce Oscillator - X-FAB XT018-0.18µm
- UCIe RX Interface
Related Blogs
- Blogging from Taiwan: TSMC and 40nm Yield
- Moore’s Law and 40nm Yield
- The Truth of TSMC 28nm Yield!
- TSMC Gets 28nm Yield Up Over 80%
Latest Blogs
- Satellite communications are no longer as secure as assumed
- Why Hardware Monitoring Needs Infrastructure, Not Just Sensors
- Why Post-Quantum Cryptography Doesn’t Replace Classical Cryptography
- The Silent Guardian of AI Compute - PUFrt Unifies Hardware Security and Memory Repair to Build the Trust Foundation for AI Factories
- Heterogeneous NPU Data Movement Tax: Intel's Own Slides Tell the Story