Taking the HyperLane with IMG A-Series
A few months back we introduced the IMG-A-Series, our latest GPU IP, packed with so much scalable, low-power graphics and compute performance we think it’s the ideal solution for a wide range of markets, from mobile, tablet and gaming to automotive, DTV and server. That’s why we called it the “GPU of Everything.”
A-Series is a significant leap forward for GPU-kind and will provide the basis for future generations of devices. To give some perspective, The Helio P95 SoC, just been announced by our friends at MediaTek is a strong mid-range chipset, featuring a PowerVR GM9446 GPU and will soon lie at the heart of some excellent, affordable devices. However, as always at Imagination, we’re looking to the future and compared to the P95, the A-Series will deliver around 2.5x the graphics performance, 8x faster AI processing or up to 60% lower power. Impressive stuff.
Originally GPUs were all about one thing, 3D graphics, and specifically fill-rate. Creating 3D triangles, calculating their position, colouring them in, processing the right ones (thank you tile-based deferred rending), and outputting them to the screen. Nowadays GPUs need to do more – it’s called “compute”. Indeed, we’ve been talking about running this on low-power GPUs for a long time.
In other words, the modern GPU needs to multi-task. To enable this, in an efficient and secure manner, we have created HyperLane Technology. Inside every A-Series, from the smallest to the very largest are eight individual hardware control lanes, each isolated in memory, enabling different tasks to be submitted to the GPU simultaneously, for fully secure GPU multitasking. It means we can have eight completely different workloads and run them simultaneously; it’s a feature that’s unique in the market.
To read the full article, click here
Related Semiconductor IP
- E-Series GPU IP
 - Arm's most performance and efficient GPU till date, offering unparalled mobile gaming and ML performance
 - 3D OpenGL ES 1.1 GPU IP core
 - 2.5D GPU
 - 2D GPU Hardware IP Core
 
Related Blogs
- The Future of Technology: Transforming Industrial IoT with Edge AI and AR
 - eUSB2 Version 2 with 4.8Gbps and the Use Cases: A Comprehensive Overview
 - Embracing the Future with Cortex-A320: A Deep Dive into the General Armv9 Architecture Adoption
 - Guarding against the threat of clock attacks with analog IP
 
Latest Blogs
- ML-DSA explained: Quantum-Safe digital Signatures for secure embedded Systems
 - Efficiency Defines The Future Of Data Movement
 - Why Standard-Cell Architecture Matters for Adaptable ASIC Designs
 - ML-KEM explained: Quantum-safe Key Exchange for secure embedded Hardware
 - Rivos Collaborates to Complete Secure Provisioning of Integrated OpenTitan Root of Trust During SoC Production