Tabula closed $104M, they’re for real. Right?
In March 2010, exactly a year ago, Tabula announced its product, the 40-nm ABAX device. The device promised a little revolution with its virtual 3D architecture, based on time multiplexing and continuous reconfiguration of its logic. At the time I mirrored Tabula’s announcement with Tier Logic’s, another PLD startup. I wondered whether Tabula could be successful, and I expressed some concerns about how much of an advantage in performance Tabula could get against a Xilinx or an Altera that can smoothly scale down their node size. Also questions were raised about the complexity of synthesizing and verifying an automatically time-multiplexed design, as well as about the extra power consumption required to reconfigure the logic with a frequency of 1.6 GHz.
Related Semiconductor IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- Parameterizable compact BCH codec
- 1G BASE-T Ethernet Verification IP
- Network-on-Chip (NoC)
- Microsecond Channel (MSC/MSC-Plus) Controller
Related Blogs
- Traditional Model of Funding Semiconductor Equipment is Broken?
- Tabula, Achronix try driving unique design advantages into solidifed FPGA sector
- Improving the EDA Funding Environment
- Tabula Closes its Doors
Latest Blogs
- Physical AI at the Edge: A New Chapter in Device Intelligence
- Rivian’s autonomy breakthrough built with Arm: the compute foundation for the rise of physical AI
- AV1 Image File Format Specification Gets an Upgrade with AVIF v1.2.0
- Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES
- Integrating Post-Quantum Cryptography (PQC) on Arty-Z7