Secret Key Generation with Physically Unclonable Functions
Yesterday, I wrote about automotive security from a big-picture level. Today let's drop down and look at some implementation approaches from the chip level. This comes from Thomas Kallstenious, who is imec's program director for security. At the imec Technology Forum, which is always the afternoon before SEMICON West, he presented some of what they are up to with some teasing hints that there would be more next year.
Physically Unclonable Functions
One problem with chip-level security is that all chips are the same. Foundries invest billions of dollars to make it so. That makes it hard to stop a successful penetration of one chip making other chips vulnerable to whatever it was you found out: you read the secret master key, for example.
Related Semiconductor IP
- PUF
- Quantum-Driven Hardware Root-of-Trust - Physical Unclonable Function (PUF)
- Fully Digital Physically Unclonable Function (PUF) - PQC Ready
- Fully-integrated 256-bit Physically Unclonable Function (PUF) with embedded reliability check
- Upgraded PUF-based Crypto Coprocessor (Compliant with TLS 1.3 / FIPS 186-5)
Related Blogs
- Physically Unclonable Functions as a Solid Foundation of Platform Security Architecture
- Data-Driven World Gets a Lift with First Two-Party PCIe v6.0 Linkup by Synopsys and Keysight
- Virage absorbs a key piece of NXP: signs for the future of IP?
- ARM and GlobalFoundries: a key relationship in the future
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?