RISC-V Is Thriving - Here's What You Need to Know
RISC-V, the open-standard Instruction Set Architecture (ISA) conceived by UC Berkeley developers in 2010, is going from strength to strength.
The RISC in RISC-V stands for Reduced Instruction Set Computer, meaning it’s designed to simplify each individual instruction given to the computer.
As RISC-V is an open standard, anyone can implement, customize, and expand the ISA to suit their requirements. RISC-V isn’t the first open ISA: Several older RISC ISAs, including POWER and SPARC, have been released into the public domain as open source. The OpenRISC project has proved popular in academic and hobbyist circles, for example. Yet none have gained the industry-wide traction of RISC-V.
What’s So Great About RISC-V?
In a word: freedom. Whether you’re a pre-seed start-up, home hobbyist, or industry heavyweight, RISC-V offers a way to design and build a chip for your device, customized to contain everything you need and nothing you don’t.
To read the full article, click here
Related Semiconductor IP
- RISC-V Debug & Trace IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- Compact Embedded RISC-V Processor
- Multi-core capable 64-bit RISC-V CPU with vector extensions
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
Related Blogs
- Customizing an Existing RISC-V Processor
- SiFive collaborates with new Intel Foundry Services to enable innovative new RISC-V computing platforms
- SiFive RISC-V Proven in 5nm Silicon
- Is RISC-V the Future?
Latest Blogs
- Silicon Insurance: Why eFPGA is Cheaper Than a Respin
- One Bit Error is Not Like Another: Understanding Failure Mechanisms in NVM
- Introducing CoreCollective for the next era of open collaboration for the Arm software ecosystem
- Integrating eFPGA for Hybrid Signal Processing Architectures
- eUSB2V2: Trends and Innovations Shaping the Future of Embedded Connectivity