Power-Efficient Recognition Systems for Embedded Applications
eural networks are hot. Las Vegas is hot, too. And there is a connection. In late June, one of the major conferences for the field, Computer Vision and Pattern Recognition (CVPR), is held there. On the Sunday before, Cadence ran a half-day training course on Power-Efficient Recognition Systems for Embedded Applications and I attended it. Trip to Vegas, yeah. Spend all day in a windowless conference room, not so much.
But the whole area is changing really fast with new developments coming all the time. Here are three things that I saw in just the last couple of days:
To read the full article, click here
Related Semiconductor IP
- Very Low Latency BCH Codec
- 5G-NTN Modem IP for Satellite User Terminals
- 400G UDP/IP Hardware Protocol Stack
- AXI-S Protocol Layer for UCIe
- HBM4E Controller IP
Related Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- ML-DSA explained: Quantum-Safe digital Signatures for secure embedded Systems
- Right Sizing AI for Embedded Applications
- Embedded Security explained: IPsec and IKEv2 for embedded Systems
Latest Blogs
- Embedded Security explained: Post-Quantum Cryptography (PQC) for embedded Systems
- Accreditation Without Compromise: Making eFPGA Assurable for Decades
- Synopsys Delivers First Complete UFS 5.0 and M‑PHY v6.0 IP Solution for Next‑Gen Storage
- World First: Synopsys MACsec IP Receives ISO/PAS 8800 Certification for Automotive and Physical AI Security
- Last-level cache has become a critical SoC design element