Today's Complex Networking Chips Demand Hardware Emulation
Project teams designing complex switches and routers have turned to hardware emulation as the foundation for their verification strategy to battle network congestion and outages.
We consumers are needy -- the three billion or so of us who use electronic devices want on-demand access to download emails, texts, videos, and all other forms of communications fast and (often) at the same time. It's little wonder, then, that networking switch and router designs have become some of the most complex of all chip designs as their sizes and complexities push north of five-hundred million ASIC-equivalent gates.
It is an axiom that the more complex the chip, the more difficult verification becomes because of all the paths that need to be verified. With embedded software nowadays implementing more and more chip functionality, thorough chip verification and validation is getting out of control. In the network domain, efficiency is critical for higher bandwidth, lower latency, and fewer network failures. Collisions are to be avoided at all costs.
To read the full article, click here
Related Semiconductor IP
- Multi-channel, multi-rate Ethernet aggregator - 10G to 400G AX (e.g., AI)
- Multi-channel, multi-rate Ethernet aggregator - 10G to 800G DX
- 200G/400G/800G Ethernet PCS/FEC
- 50G/100G MAC/PCS/FEC
- 25G/10G/SGMII/ 1000BASE-X PCS and MAC
Related Blogs
- The Future of Hardware Emulation
- A Great Match: SoC Verification & Hardware Emulation
- Hardware Emulation: One Verification Tool, Unending Possibilities
- Risk Avoidance, Hardware Emulation Style