A Great Match: SoC Verification & Hardware Emulation
Design and verification project groups have a new tool in the arsenal that will enable better hardware emulation results, greater efficiency, and increased productivity.
More than once, I have heard design and verification project groups complain about the lack of a unified and consistent SoC (system-on-chip) verification process. Almost all of them were juggling the wide range of verification technologies in their environments, including simulation, simulation acceleration, emulation, prototyping, and silicon validation -- and they certainly were not juggling efficiently. This has gone on for years and is only getting more complicated.
To read the full article, click here
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related Blogs
- T&VS delivers Emulation and Validation services for Mobile SoC
- Leveraging a Unified Emulation and Prototyping System to Address Verification Requirements Across the Chip Development Cycle
- Execute Your Hardware Verification Campaign in the Cloud - a Verification Engineer's Perspective
- Portable Stimulus: The Next Big Leap In SoC Verification
Latest Blogs
- lowRISC Tackles Post-Quantum Cryptography Challenges through Research Collaborations
- How to Solve the Size, Weight, Power and Cooling Challenge in Radar & Radio Frequency Modulation Classification
- Programmable Hardware Delivers 10,000X Improvement in Verification Speed over Software for Forward Error Correction
- The Integrated Design Challenge: Developing Chip, Software, and System in Unison
- Introducing Mi-V RV32 v4.0 Soft Processor: Enhanced RISC-V Power