A Great Match: SoC Verification & Hardware Emulation
November 3, 2014
Design and verification project groups have a new tool in the arsenal that will enable better hardware emulation results, greater efficiency, and increased productivity.
More than once, I have heard design and verification project groups complain about the lack of a unified and consistent SoC (system-on-chip) verification process. Almost all of them were juggling the wide range of verification technologies in their environments, including simulation, simulation acceleration, emulation, prototyping, and silicon validation -- and they certainly were not juggling efficiently. This has gone on for years and is only getting more complicated.
To read the full article, click here
Related Semiconductor IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
- 50G PON LDPC Encoder/Decoder
- UALink Controller
- RISC-V Debug & Trace IP
Related Blogs
- A Comparison on Different AMBA 5 CHI Verification IPs
- Accelerating Your Development: Simplify SoC I/O with a Single Multi-Protocol SerDes IP
- Maximizing SoC Longevity with PCIe 3.0: A Designer’s Guide
- Powering Up Efficiency: A Deep Dive into CXL L0p and its Verification
Latest Blogs
- Deploying StrongSwan on an Embedded FPGA Platform, IPsec/IKEv2 on Arty Z7 with PetaLinux and PQC
- The Rise of Physical AI: When Intelligence Enters the Real World
- Can Open-Source ISAs Catalyze Smart Manufacturing?
- The Future of AI is Modular: Why the SiFive-NVIDIA Milestone Matters
- Heterogeneous Multicore using Cadence IP