Moore's Law and Semiconductor Design and Manufacturing
March 14, 2011
The semiconductor design and manufacturing challenges at 40nm and 28nm are a direct result of Moore’s Law, the climbing transistor count and shrinking geometries. It’s a process AND design issue and the interaction is at the transistor level. Transistors may be shrinking, but atoms aren’t. So now it actually matters when even a few atoms are out of place. So process variations, whether they are statistical, proximity, or otherwise, have got to be thoughtfully accounted for, if we are to achieve low-power, high-performance, and high yield design goals.
To read the full article, click here
Related Semiconductor IP
- 50MHz to 800MHz Integer-N RC Phase-Locked Loop on SMIC 55nm LL
- Simulation VIP for AMBA CHI-C2C
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- USB 20Gbps Device Controller
- SM4 Cipher Engine
Related Blogs
- How Is the Semiconductor Industry Handling Scaling: Is Moore's Law Still Alive?
- Reshoring Semiconductor Manufacturing
- Semiconductor Growth from AI-Driven Design Productivity
- Can the Semiconductor Industry Overcome Thermal Design Challenges in Multi-Die Systems?
Latest Blogs
- Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet
- Arm and Synopsys: Delivering an Integrated, Nine-Stage “Silicon-to-System” Chip Design Flow
- Accelerate Automotive System Design with Cadence AI-Driven DSPs
- What Makes FPGA Architecture Ideal for Ultra-Low-Latency Systems?
- Introducing agileSecure anti-tamper security portfolio