Lead Times Up, Inventories Low, Double-Ordering Rife, Capacity Strained
June 23, 2010
The chip upturn is following its traditional pattern - inventory levels remain low, double ordering appears common, lead times are lengthening and capacity is straining to keep up with demand..
"Chip makers and other participants in the chain are shorter on supply than is widely perceived," says iSuppli's Carlo Ciriello.
To read the full article, click here
Related Semiconductor IP
- Network-on-Chip (NoC)
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- UCIe PHY (Die-to-Die) IP
- UCIe-S 64GT/s PHY IP
- UA Link DL IP core
Related Blogs
- Could China Take the Lead in Installed 300mm Capacity?
- Netbook Chip-Set Orders To Max Out Capacity At TSMC & UMC
- Advanced Fab Capacity Utilisation Tops 90%
- TSMC UMC Lead Semiconductor Recovery - Record Year in 2010
Latest Blogs
- Design specification: The cornerstone of an ASIC collaboration
- The importance of ADCs in low-power electrocardiography ASICs
- VESA Adaptive-Sync V2 Operation in DisplayPort VIP
- Design, Verification, and Software Development Decisions Require a Single Source of Truth
- CAVP-Validated Post-Quantum Cryptography