The realities of IP reuse
August 17, 2011
Long touted as a silver bullet, IP reuse often fails to live up to expectations when it comes to increasing semiconductor R&D productivity and throughput. That’s because most IC development teams fail to recognize a critical non-linear relationship exists between the amount of circuitry they modify or “improve” in pre-existing IP blocks and the effort the engineering team expends in making those modified blocks operate properly in the target IC. Bottom line: small changes can have a disproportionate impact on project effort. Not being fully cognizant of the specifics of this non-linear behavior is a common trap into which myriad engineering teams unwittingly fall.
To read the full article, click here
Related Semiconductor IP
- Power-OK Monitor
- RISC-V-Based, Open Source AI Accelerator for the Edge
- Securyzr™ neo Core Platform
- 112G Multi-SerDes
- SHA3 Cryptographic Hash Cores
Related Blogs
- Tips on Using e Macros to Raise Abstraction and Facilitate Reuse
- Why your Internal IP Reuse Strategy is not Working
- How Will High-Level Synthesis Affect the Make vs. Buy vs. Re-use Decision?
- Think Different, Innovate by Reuse
Latest Blogs
- Why Anti-tamper Sensors Matter: Agile Analog and Rambus Deliver Comprehensive Security Solution
- Automotive Ethernet with Comcores – Safety, Quality and ASIL certification of IP
- A Comparison on Different AMBA 5 CHI Verification IPs
- Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum
- Accelerating Development Cycles and Scalable, High-Performance On-Device AI with New Arm Lumex CSS Platform