The realities of IP reuse
August 17, 2011
Long touted as a silver bullet, IP reuse often fails to live up to expectations when it comes to increasing semiconductor R&D productivity and throughput. That’s because most IC development teams fail to recognize a critical non-linear relationship exists between the amount of circuitry they modify or “improve” in pre-existing IP blocks and the effort the engineering team expends in making those modified blocks operate properly in the target IC. Bottom line: small changes can have a disproportionate impact on project effort. Not being fully cognizant of the specifics of this non-linear behavior is a common trap into which myriad engineering teams unwittingly fall.
Related Semiconductor IP
- JESD204D Transmitter and Receiver IP
- 100G UDP IP Stack
- Frequency Synthesizer
- Temperature Sensor IP
- LVDS Driver/Buffer
Related Blogs
- Tips on Using e Macros to Raise Abstraction and Facilitate Reuse
- Design Reuse: It's Harder Than it Looks
- Why your Internal IP Reuse Strategy is not Working
- How Will High-Level Synthesis Affect the Make vs. Buy vs. Re-use Decision?
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?