IP Quality: Foundation of a Successful Ecosystem
Talking about Design IP (I mean successful Design IP) lead you to quickly pronounce the two magic key words: Quality and Ecosystem. Those who remember the IP emergence in the mid 90’s know very well why Quality has to be a prerequisite when dealing with Design IP, as they probably have paid the price of mediocre IP quality at that time. More recently, business analysts have realized that the foundation for a successful IP based business was linked to building a complete Ecosystem, just think about the 1000 ARM partners...
As a matter of fact, some of these partners are heavyweight, like Taiwan based TSMC, that any IP vendor would like to count within it IP Ecosystem. That’s why TSMC has created, back in 2000, the TSMC9000 program as one of the pillar of Open Integration Platform (OIP) ecosystem. TSMC9000 clearly defined goal is to check for, assess and audit the quality of Design IP part of OIP ecosystem.
Related Semiconductor IP
- 112G PHY, TSMC N7 x4, North/South (vertical) poly orientation
- 112G Ethernet PHY, TSMC N7 x4, North/South (vertical) poly orientation
- 112G Ethernet PHY, TSMC N7 x2, North/South (vertical) poly orientation
- 112G Ethernet PHY, TSMC N7 x1, North/South (vertical) poly orientation
- 112G Ethernet PHY, TSMC N6 x2, North/South (vertical) poly orientation
Related Blogs
- Ensuring IP Quality for a Better IP Experience
- Neoverse S3 System IP: A Foundation for Confidential Compute and Multi-chiplet Infrastructure SoCs
- World IP Day: A Time to Reflect on the Value of Semiconductor IP
- UCIe Heralds a Robust Chiplet Ecosystem for a New Era of SoC Innovation
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?