IP integration: Is it the real system-level design?
The search for productivity in SOC (system-on-chip) design is a search for balance between abstraction and automation. Greater abstraction at a step in the design flow means fewer design elements to process. Greater automation means that each element requires less human attention. Ideally, designers could capture an abstract representation of an SOC’s intended behavior, verify that the representation describes the desired chip, and push a button to tape-out. We are not yet there.
For years, some enthusiasts have promoted high-level design languages—often dialects of C—as the path to greater abstraction. Except in a few categories of architectural elements, however, it has been difficult to move the design beyond behavioral or transaction-level representation and into the implementation flow. “High-level synthesis is still very domain-specific,” says Ken Wagner, PMC-Sierra’s vice president of engineering. Without synthesis, designers must recode the high-level version by hand into RTL (register-transfer-level) logic.
Related Semiconductor IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
- High Speed Ethernet 2/4/8-Lane 200G/400G PCS
Related Blogs
- Design IP Sales Grew 16.7% in 2020, Best Growth Rate Ever!
- Design IP Sales Grew 19.4% in 2021, confirm 2016-2021 CAGR of 9.8%
- Reduce Integration Risks for High-Speed Applications with PCIe 5.0-Compliant Synopsys IP
- Design IP Sales Grew 20.2% in 2022 after 19.4% in 2021 and 16.7% in 2020!
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?