IP integration: Is it the real system-level design?
The search for productivity in SOC (system-on-chip) design is a search for balance between abstraction and automation. Greater abstraction at a step in the design flow means fewer design elements to process. Greater automation means that each element requires less human attention. Ideally, designers could capture an abstract representation of an SOC’s intended behavior, verify that the representation describes the desired chip, and push a button to tape-out. We are not yet there.
For years, some enthusiasts have promoted high-level design languages—often dialects of C—as the path to greater abstraction. Except in a few categories of architectural elements, however, it has been difficult to move the design beyond behavioral or transaction-level representation and into the implementation flow. “High-level synthesis is still very domain-specific,” says Ken Wagner, PMC-Sierra’s vice president of engineering. Without synthesis, designers must recode the high-level version by hand into RTL (register-transfer-level) logic.
To read the full article, click here
Related Semiconductor IP
- Flexible Pixel Processor Video IP
- Complex Digital Up Converter
- Bluetooth Low Energy 6.0 Digital IP
- Verification IP for Ultra Ethernet (UEC)
- MIPI SWI3S Manager Core IP
Related Blogs
- Reduce Integration Risks for High-Speed Applications with PCIe 5.0-Compliant Synopsys IP
- Design IP Sales Grew 20.2% in 2022 after 19.4% in 2021 and 16.7% in 2020!
- Understanding USB IP and Its Role in SOC Integration
- I3C IP: Enabling Efficient Communication and Sensor Integration
Latest Blogs
- CNNs and Transformers: Decoding the Titans of AI
- How is RISC-V’s open and customizable design changing embedded systems?
- Imagination GPUs now support Vulkan 1.4 and Android 16
- From "What-If" to "What-Is": Cadence IP Validation for Silicon Platform Success
- Accelerating RTL Design with Agentic AI: A Multi-Agent LLM-Driven Approach