IEDM: The Big Decisions for 5nm
December 12, 2016
The Sunday of IEDM there were two all-day short courses. The one I attended was Technology Options for the 5nm Node. It was organized by An Steegen of imec. I am not going to attempt to cover the entire day's presentations in a short post like this, but the topics covered included lithography, channel materials, transistor options beyond FinFET, low-resistance contacts, minimizing parasitics in the metal stack, and metrology.
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