Genus and Innovus: Compus and Spatial
Yesterday I covered the first part of Chuck Alpert's presentation on the upcoming-any-day-now release of Genus (19.1 i you're counting). Today I'll dig into the details a bit more.
In the new release, there is a next-generation compiler called Compus (pronounced like compass, my favorite extinct EDA company). This very aggressively flattens the levels of logic. As an example, iChuck had a huge priority encoder might end up with 92,000 instances at elaboration, but can be optimized down to 29,000.
Compus aggressively uses multiple CPUs to try different architectures and so guides the synthesis process to the correct microarchitecture, especially opt. This is analogous to what the user might do in prior generations of synthesis, manually getting the tool to try different ideas and picking the one that looked the most promising for doing all the detailed optimization.
To read the full article, click here
Related Semiconductor IP
- Flexible Pixel Processor Video IP
- Complex Digital Up Converter
- Bluetooth Low Energy 6.0 Digital IP
- Verification IP for Ultra Ethernet (UEC)
- MIPI SWI3S Manager Core IP
Related Blogs
- Evaluating Spatial Audio - Part 2 - Creating and Curating Content for Testing
- Exploring the XSPI PHY: Technical Characteristics, Architectural Challenges, and Arasan Chip Systems' Solution
- ETAS and Rambus Plan Joint Development of Automotive Cybersecurity Solutions
- How User Behaviour and Applications are Shaping Affordable Smartphones
Latest Blogs
- CNNs and Transformers: Decoding the Titans of AI
- How is RISC-V’s open and customizable design changing embedded systems?
- Imagination GPUs now support Vulkan 1.4 and Android 16
- From "What-If" to "What-Is": Cadence IP Validation for Silicon Platform Success
- Accelerating RTL Design with Agentic AI: A Multi-Agent LLM-Driven Approach