Verification Panel, Part 3: Stretching Formal
In Part 1 of this panel discussion on verification, the experts talked about the state of verification and the progress that has been made.
In Part 2 the subject broadened to the increasing areas in which verification has to be performed, including power and software. In this third part the discussion turns to the how far formal methods can go in addressing the challenges facing SoC design.
Taking part in this discussion are: Paul Martin, senior manager of debug, trace, and performance modeling at ARM; Rajeev Ranjan, CTO, and Oz Levia, vice president of marketing and business development at Jasper Design Automation; Harry Foster, chief verification scientist at Mentor Graphics; and Viresh Paruthi, senior technical staff member at IBM.
To read the full article, click here
Related Semiconductor IP
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- NPU IP Core for Mobile
Related Blogs
- How to Speed Up Simulation Coverage Closure with Formal Verification Tools
- Raising RISC-V processor quality with formal verification
- Formal verification best practices to reach your targets
- Formal verification best practices: investigating a deadlock
Latest Blogs
- Cadence Leads the Way at PCI-SIG DevCon 2025 with Groundbreaking PCIe 7.0 Demos
- Introducing the Akeana 1000 Series Processors
- How fast a GPU do you need for your user interface?
- PCIe 6.x and 112 Gbps Ethernet: Synopsys and TeraSignal Achieve Optical Interconnect Breakthroughs
- Powering the Future of RF: Falcomm and GlobalFoundries at IMS 2025