FD-SOI Can Deliver Leading-Edge European IC Process Technology
May 22, 2013
Next month customers can start prototyping on STMicroelectronics’ 28nm FD-SOI process which delivers 30% better performance than 28nm bulk CMOS, according to ST’s CTO and CMO Jean-Marc Chery.
From there the planned progress down the micron trail to 14nm is dramatic: another 30% improvement at the same operating voltage at 14nm; a 50% reduction in power at the same speed at 14nm; and a 40% reduction in die area at 14nm.
The figures can be further improved by biassing. Forward body bias on 14nm FD-SOI gives another 15% performance at the same operating voltage; reverse body bias reduces power by another 10% while maintaining the same speed.
To read the full article, click here
Related Semiconductor IP
- Network-on-Chip (NoC)
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- DVB-S2 Demodulator
- UCIe PHY (Die-to-Die) IP
- UCIe-S 64GT/s PHY IP
Related Blogs
- Can "Less than Moore" FDSOI provides better ROI for Mobile IC?
- Minima's Low Energy IP Garners Support from the European Innovation Council Accelerator
- Management of Projects - Is it really working?
- ARM 1176 in IBM SOI process demonstrates a cell-based flow
Latest Blogs
- Enabling End-to-End EDA Flow on Arm-Based Compute for Infrastructure Flexibility
- Real PPA improvements from analog IC migration
- Design specification: The cornerstone of an ASIC collaboration
- The importance of ADCs in low-power electrocardiography ASICs
- VESA Adaptive-Sync V2 Operation in DisplayPort VIP