FD-SOI Can Deliver Leading-Edge European IC Process Technology
Next month customers can start prototyping on STMicroelectronics’ 28nm FD-SOI process which delivers 30% better performance than 28nm bulk CMOS, according to ST’s CTO and CMO Jean-Marc Chery.
From there the planned progress down the micron trail to 14nm is dramatic: another 30% improvement at the same operating voltage at 14nm; a 50% reduction in power at the same speed at 14nm; and a 40% reduction in die area at 14nm.
The figures can be further improved by biassing. Forward body bias on 14nm FD-SOI gives another 15% performance at the same operating voltage; reverse body bias reduces power by another 10% while maintaining the same speed.
To read the full article, click here
Related Semiconductor IP
- HBM4 PHY IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
- HBM4 Controller IP
- IPSEC AES-256-GCM (Standalone IPsec)
Related Blogs
- Can "Less than Moore" FDSOI provides better ROI for Mobile IC?
- Minima's Low Energy IP Garners Support from the European Innovation Council Accelerator
- Management of Projects - Is it really working?
- ARM 1176 in IBM SOI process demonstrates a cell-based flow
Latest Blogs
- ReRAM in Automotive SoCs: When Every Nanosecond Counts
- AndeSentry – Andes’ Security Platform
- Formally verifying AVX2 rejection sampling for ML-KEM
- Integrating PQC into StrongSwan: ML-KEM integration for IPsec/IKEv2
- Breaking the Bandwidth Barrier: Enabling Celestial AI’s Photonic Fabric™ with Custom ESD IP on TSMC’s 5nm Platform